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| author | Walter Ji <walter.ji@oss.cipunited.com> | 2023-11-17 15:13:21 +0800 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2024-01-06 13:51:26 +0000 |
| commit | b2172ed7d785ff1cd816d93cbed30afb45f1402b (patch) | |
| tree | 9dc96a126caba27e0fb3d2ed4f409b038f93ce26 /src/target/mips32.h | |
| parent | 7de4b1202d5049dead386b3bcfa238b299f7c742 (diff) | |
| download | riscv-openocd-b2172ed7d785ff1cd816d93cbed30afb45f1402b.zip riscv-openocd-b2172ed7d785ff1cd816d93cbed30afb45f1402b.tar.gz riscv-openocd-b2172ed7d785ff1cd816d93cbed30afb45f1402b.tar.bz2 | |
target/mips32: update coprocessor 0 command
Update mips32 cp0 command, it accepts cp0 reg names now.
Updated mips32 cp0 description.
Change-Id: Ib23dd13519def77a657c9c5bb039276746207b9b
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7905
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Diffstat (limited to 'src/target/mips32.h')
| -rw-r--r-- | src/target/mips32.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/target/mips32.h b/src/target/mips32.h index 1bb75da..46c2ad9 100644 --- a/src/target/mips32.h +++ b/src/target/mips32.h @@ -84,7 +84,7 @@ /* CP1 FIR register fields */ #define MIPS32_CP1_FIR_F64_SHIFT 22 -static const struct { +static const struct mips32_cp0 { unsigned int reg; unsigned int sel; const char *name; @@ -202,7 +202,7 @@ static const struct { {31, 3, "kscratch2", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP}, }; -#define MIPS32NUMCP0REGS ((int)ARRAY_SIZE(mips32_cp0_regs)) +#define MIPS32NUMCP0REGS (ARRAY_SIZE(mips32_cp0_regs)) /* Insert extra NOPs after the DRET instruction on exit from debug. */ #define EJTAG_QUIRK_PAD_DRET BIT(0) @@ -397,6 +397,12 @@ struct mips32_common { int fdc; int semihosting; + /* The cp0 registers implemented on different processor cores could be different, too. + * Here you can see most of the registers are implemented on interAptiv, which is + * a 2c4t SMP processor, it has more features than M-class processors, like vpe + * and other config registers for multhreading. */ + uint32_t cp0_mask; + /* FPU enabled (cp0.status.cu1) */ bool fpu_enabled; /* FPU mode (cp0.status.fr) */ |