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| author | Christian Hoff <christian.hoff@advantest.com> | 2020-11-23 14:34:56 +0100 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-03-19 21:57:43 +0000 |
| commit | 6c0151623cb09da6a80655cedf568db927ae2d93 (patch) | |
| tree | 4b14f8cafac313e08f7ac1b2dbcad788f883f040 /src/target/image.c | |
| parent | 25218e8935037367e419219f8c855d92a3163023 (diff) | |
| download | riscv-openocd-6c0151623cb09da6a80655cedf568db927ae2d93.zip riscv-openocd-6c0151623cb09da6a80655cedf568db927ae2d93.tar.gz riscv-openocd-6c0151623cb09da6a80655cedf568db927ae2d93.tar.bz2 | |
aarch64: add support for "reset halt"
Support halting the CPU directly after a reset. If halt is
requested, the CPU stops directly at the reset vector, before
any code is executed.
This functionality was implemented using the Reset Catch
debug event.
Change-Id: If90d54c088442340376f0b588ba10267ea8e7327
Signed-off-by: Christian Hoff <christian.hoff@advantest.com>
Reviewed-on: http://openocd.zylin.com/5947
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Diffstat (limited to 'src/target/image.c')
0 files changed, 0 insertions, 0 deletions