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| author | Liviu Ionescu <ilg@livius.net> | 2018-05-13 18:39:06 +0300 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-06-04 09:16:08 +0100 |
| commit | 2517bae6c1438350255dca63e7d1c1e06c64b6bb (patch) | |
| tree | 707cce397bf68d1fd040f7f2a4c17e722257fdcd /src/target/image.c | |
| parent | cdf1e826eb23c29de1019ce64125f644f01b0afe (diff) | |
| download | riscv-openocd-2517bae6c1438350255dca63e7d1c1e06c64b6bb.zip riscv-openocd-2517bae6c1438350255dca63e7d1c1e06c64b6bb.tar.gz riscv-openocd-2517bae6c1438350255dca63e7d1c1e06c64b6bb.tar.bz2 | |
Rework/update ARM semihosting
In 2016, ARM released the second edition of the semihosting specs
("Semihosting for AArch32 and AArch64"), adding support for 64-bits.
To ease the reuse of the semihosting logic for other platforms
(like RISC-V), the semihosting code was isolated from the ARM
target and updated to the latest specs.
The new code is already in use since January (in GNU MCU Eclipse
OpenOCD) and no problems were reported, neither for ARM nor for
RISC-V targets, after more than 7K downloads.
The 2 new files were formatted with uncrustify.
Change-Id: Ie84dbd86a547323bb8a5d24eab68fc7dad013d96
Signed-off-by: Liviu Ionescu <ilg@livius.net>
Reviewed-on: http://openocd.zylin.com/4518
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/image.c')
0 files changed, 0 insertions, 0 deletions