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| author | Spencer Oliver <spen@spen-soft.co.uk> | 2013-09-11 12:33:32 +0100 |
|---|---|---|
| committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2013-09-21 20:08:38 +0000 |
| commit | 80a94681de4c304ed8d550d4da547cdc523d2207 (patch) | |
| tree | 45e9403d4a5b9f88d71d183768469b86b8e07186 /src/target/hla_target.c | |
| parent | d14058db0aee78de9a9bc5bddeafe7844ac01587 (diff) | |
| download | riscv-openocd-80a94681de4c304ed8d550d4da547cdc523d2207.zip riscv-openocd-80a94681de4c304ed8d550d4da547cdc523d2207.tar.gz riscv-openocd-80a94681de4c304ed8d550d4da547cdc523d2207.tar.bz2 | |
armv7m: remove gdb register hacks
Now that we support the target description format we do not need
these hacks anymore, we can now tell gdb what registers we support.
Change-Id: Ie774231d296420b35efcf708bc4435475c87ff5e
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1617
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'src/target/hla_target.c')
| -rw-r--r-- | src/target/hla_target.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/target/hla_target.c b/src/target/hla_target.c index 078ac64..2db04f8 100644 --- a/src/target/hla_target.c +++ b/src/target/hla_target.c @@ -157,18 +157,6 @@ static int adapter_store_core_reg_u32(struct target *target, LOG_DEBUG("%s", __func__); -#ifdef ARMV7_GDB_HACKS - /* If the LR register is being modified, make sure it will put us - * in "thumb" mode, or an INVSTATE exception will occur. This is a - * hack to deal with the fact that gdb will sometimes "forge" - * return addresses, and doesn't set the LSB correctly (i.e., when - * printing expressions containing function calls, it sets LR = 0.) - * Valid exception return codes have bit 0 set too. - */ - if (num == ARMV7M_R14) - value |= 0x01; -#endif - /* NOTE: we "know" here that the register identifiers used * in the v7m header match the Cortex-M3 Debug Core Register * Selector values for R0..R15, xPSR, MSP, and PSP. |