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| author | Marc Schink <openocd-dev@marcschink.de> | 2019-02-26 14:09:22 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2019-03-06 16:17:24 +0000 |
| commit | ffd8e2b630600703805c6500f92da8775aa88d10 (patch) | |
| tree | 4e1217a1c275ce006be80e7bb50cf43a5f408ac5 /src/target/feroceon.c | |
| parent | 61a55f6278f73332ea55ff08194d0c41b9136ecd (diff) | |
| download | riscv-openocd-ffd8e2b630600703805c6500f92da8775aa88d10.zip riscv-openocd-ffd8e2b630600703805c6500f92da8775aa88d10.tar.gz riscv-openocd-ffd8e2b630600703805c6500f92da8775aa88d10.tar.bz2 | |
target/feroceon: Use 'bool' data type
Change-Id: I30b8d07ee198e8f67cd98f83c4bec15bcfe8be08
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4967
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src/target/feroceon.c')
| -rw-r--r-- | src/target/feroceon.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 21963e5..4a6c6dc 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -532,8 +532,8 @@ static int feroceon_bulk_write_memory(struct target *target, /* set up target address in r0 */ buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address); - arm->core_cache->reg_list[0].valid = 1; - arm->core_cache->reg_list[0].dirty = 1; + arm->core_cache->reg_list[0].valid = true; + arm->core_cache->reg_list[0].dirty = true; arm->core_state = ARM_STATE_ARM; embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); @@ -575,12 +575,12 @@ static int feroceon_bulk_write_memory(struct target *target, /* restore target state */ for (i = 0; i <= 5; i++) { buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]); - arm->core_cache->reg_list[i].valid = 1; - arm->core_cache->reg_list[i].dirty = 1; + arm->core_cache->reg_list[i].valid = true; + arm->core_cache->reg_list[i].dirty = true; } buf_set_u32(arm->pc->value, 0, 32, save[i]); - arm->pc->valid = 1; - arm->pc->dirty = 1; + arm->pc->valid = true; + arm->pc->dirty = true; arm->core_state = core_state; return retval; |