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| author | Erhan Kurubas <erhan.kurubas@espressif.com> | 2022-06-30 13:14:27 +0300 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-09-03 21:27:17 +0000 |
| commit | bea4d6590356f4a9ef0bcb6b270943e565852f0e (patch) | |
| tree | a7e84dddfb2a990f05a2e502b8095df82a1260ce /src/target/espressif/esp32s3.c | |
| parent | 7dc4be3157d666ef05905151b7b4d0f05778b08a (diff) | |
| download | riscv-openocd-bea4d6590356f4a9ef0bcb6b270943e565852f0e.zip riscv-openocd-bea4d6590356f4a9ef0bcb6b270943e565852f0e.tar.gz riscv-openocd-bea4d6590356f4a9ef0bcb6b270943e565852f0e.tar.bz2 | |
target/espressif: add semihosting support
ARM semihosting + some custom syscalls implemented for
Espressif chips (ESP32, ESP32-S2, ESP32-S3)
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ic8174cf1cd344fa16d619b7b8405c9650e869443
Reviewed-on: https://review.openocd.org/c/openocd/+/7074
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src/target/espressif/esp32s3.c')
| -rw-r--r-- | src/target/espressif/esp32s3.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/src/target/espressif/esp32s3.c b/src/target/espressif/esp32s3.c index b870059..0da8552 100644 --- a/src/target/espressif/esp32s3.c +++ b/src/target/espressif/esp32s3.c @@ -13,6 +13,7 @@ #include <target/target.h> #include <target/target_type.h> #include <target/smp.h> +#include <target/semihosting_common.h> #include "assert.h" #include "esp_xtensa_smp.h" @@ -302,7 +303,7 @@ static int esp32s3_virt2phys(struct target *target, static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target) { - return esp_xtensa_target_init(cmd_ctx, target); + return esp_xtensa_smp_target_init(cmd_ctx, target); } static const struct xtensa_debug_ops esp32s3_dbg_ops = { @@ -321,6 +322,10 @@ static const struct esp_xtensa_smp_chip_ops esp32s3_chip_ops = { .on_halt = esp32s3_on_halt }; +static const struct esp_semihost_ops esp32s3_semihost_ops = { + .prepare = esp32s3_disable_wdts +}; + static int esp32s3_target_create(struct target *target, Jim_Interp *interp) { struct xtensa_debug_module_config esp32s3_dm_cfg = { @@ -340,7 +345,8 @@ static int esp32s3_target_create(struct target *target, Jim_Interp *interp) int ret = esp_xtensa_smp_init_arch_info(target, &esp32s3->esp_xtensa_smp, &esp32s3_dm_cfg, - &esp32s3_chip_ops); + &esp32s3_chip_ops, + &esp32s3_semihost_ops); if (ret != ERROR_OK) { LOG_ERROR("Failed to init arch info!"); free(esp32s3); @@ -363,6 +369,13 @@ static const struct command_registration esp32s3_command_handlers[] = { .usage = "", .chain = smp_command_handlers, }, + { + .name = "arm", + .mode = COMMAND_ANY, + .help = "ARM Command Group", + .usage = "", + .chain = semihosting_common_handlers + }, COMMAND_REGISTRATION_DONE }; |