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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-18 14:49:22 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-18 14:49:22 -0800 |
| commit | 94dba423137d25fbe898fe7b04c451c6225a0079 (patch) | |
| tree | 8514461c03e97dc8f0412f2cf8396200b90ee531 /src/target/cortex_a8.c | |
| parent | f5093e160534c269b8bc3590f5809ed3baead56f (diff) | |
| download | riscv-openocd-94dba423137d25fbe898fe7b04c451c6225a0079.zip riscv-openocd-94dba423137d25fbe898fe7b04c451c6225a0079.tar.gz riscv-openocd-94dba423137d25fbe898fe7b04c451c6225a0079.tar.bz2 | |
ARM: add a default full_context() method
If the core doesn't provide an optimized version of this
method, provide one without core-specific optimizations.
Use this to make Cortex-A8 support the "arm reg" command.
Related: make the two register access methods properly static,
have the "set" log a "not halted" error too, and make sure
that the "valid" flag is set on successful reads.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/cortex_a8.c')
| -rw-r--r-- | src/target/cortex_a8.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index b69f182..37e5e3e 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -1456,10 +1456,6 @@ int cortex_a8_init_arch_info(struct target *target, struct arm *armv4_5 = &armv7a->armv4_5_common; struct swjdp_common *swjdp = &armv7a->swjdp_info; - /* REVISIT v7a setup should be in a v7a-specific routine */ - armv4_5_init_arch_info(target, armv4_5); - armv7a->common_magic = ARMV7_COMMON_MAGIC; - /* Setup struct cortex_a8_common */ cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; armv4_5->arch_info = armv7a; @@ -1503,12 +1499,10 @@ LOG_DEBUG(" "); armv4_5->read_core_reg = cortex_a8_read_core_reg; armv4_5->write_core_reg = cortex_a8_write_core_reg; -// armv4_5->full_context = arm7_9_full_context; -// armv4_5->load_core_reg_u32 = cortex_a8_load_core_reg_u32; -// armv4_5->store_core_reg_u32 = cortex_a8_store_core_reg_u32; -// armv4_5->read_core_reg = armv4_5_read_core_reg; /* this is default */ -// armv4_5->write_core_reg = armv4_5_write_core_reg; + /* REVISIT v7a setup should be in a v7a-specific routine */ + armv4_5_init_arch_info(target, armv4_5); + armv7a->common_magic = ARMV7_COMMON_MAGIC; target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target); |