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| author | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2023-10-31 21:13:46 +0300 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-12-01 22:23:13 +0000 |
| commit | 73d62f3f0cd4cb3fb6975d4223bf44b35a0e1479 (patch) | |
| tree | d00e678da0ad376b8dd78550198511f3414500dd /src/target/cortex_a.c | |
| parent | 15038ab51a3c5811f7ff95c1f995c6e9dfe7d3d0 (diff) | |
| download | riscv-openocd-73d62f3f0cd4cb3fb6975d4223bf44b35a0e1479.zip riscv-openocd-73d62f3f0cd4cb3fb6975d4223bf44b35a0e1479.tar.gz riscv-openocd-73d62f3f0cd4cb3fb6975d4223bf44b35a0e1479.tar.bz2 | |
target: clarify usage of `coreid`
By definition in `target/target.h`, `coreid` is not a unique identifier
of a target -- it can be the same for targets on different TAPs.
Change-Id: Ifce78da55fffe28dd8b6b06ecae7d8c4e305c0a2
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7997
Tested-by: jenkins
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src/target/cortex_a.c')
| -rw-r--r-- | src/target/cortex_a.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index ba3349d..7fa0c4e 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -2989,29 +2989,29 @@ static int cortex_a_examine_first(struct target *target) armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg); if (retval != ERROR_OK) return retval; - LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg); + LOG_TARGET_DEBUG(target, "DBGPRSR 0x%" PRIx32, dbg_osreg); if ((dbg_osreg & PRSR_POWERUP_STATUS) == 0) { - LOG_ERROR("target->coreid %" PRId32 " powered down!", target->coreid); + LOG_TARGET_ERROR(target, "powered down!"); target->state = TARGET_UNKNOWN; /* TARGET_NO_POWER? */ return ERROR_TARGET_INIT_FAILED; } if (dbg_osreg & PRSR_STICKY_RESET_STATUS) - LOG_DEBUG("target->coreid %" PRId32 " was reset!", target->coreid); + LOG_TARGET_DEBUG(target, "was reset!"); /* Read DBGOSLSR and check if OSLK is implemented */ retval = mem_ap_read_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_OSLSR, &dbg_osreg); if (retval != ERROR_OK) return retval; - LOG_DEBUG("target->coreid %" PRId32 " DBGOSLSR 0x%" PRIx32, target->coreid, dbg_osreg); + LOG_TARGET_DEBUG(target, "DBGOSLSR 0x%" PRIx32, dbg_osreg); /* check if OS Lock is implemented */ if ((dbg_osreg & OSLSR_OSLM) == OSLSR_OSLM0 || (dbg_osreg & OSLSR_OSLM) == OSLSR_OSLM1) { /* check if OS Lock is set */ if (dbg_osreg & OSLSR_OSLK) { - LOG_DEBUG("target->coreid %" PRId32 " OSLock set! Trying to unlock", target->coreid); + LOG_TARGET_DEBUG(target, "OSLock set! Trying to unlock"); retval = mem_ap_write_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_OSLAR, @@ -3022,8 +3022,7 @@ static int cortex_a_examine_first(struct target *target) /* if we fail to access the register or cannot reset the OSLK bit, bail out */ if (retval != ERROR_OK || (dbg_osreg & OSLSR_OSLK) != 0) { - LOG_ERROR("target->coreid %" PRId32 " OSLock sticky, core not powered?", - target->coreid); + LOG_TARGET_ERROR(target, "OSLock sticky, core not powered?"); target->state = TARGET_UNKNOWN; /* TARGET_NO_POWER? */ return ERROR_TARGET_INIT_FAILED; } @@ -3036,13 +3035,11 @@ static int cortex_a_examine_first(struct target *target) return retval; if (dbg_idpfr1 & 0x000000f0) { - LOG_DEBUG("target->coreid %" PRId32 " has security extensions", - target->coreid); + LOG_TARGET_DEBUG(target, "has security extensions"); armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT; } if (dbg_idpfr1 & 0x0000f000) { - LOG_DEBUG("target->coreid %" PRId32 " has virtualization extensions", - target->coreid); + LOG_TARGET_DEBUG(target, "has virtualization extensions"); /* * overwrite and simplify the checks. * virtualization extensions require implementation of security extension |