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| author | Julien Massot <julien.massot@iot.bzh> | 2022-01-12 09:41:13 +0100 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-01-29 18:20:48 +0000 |
| commit | 93f2276cdd99ad9e9d844150553621ea5d8524dd (patch) | |
| tree | 42f673b54b5a20d7916be0f805d694be561e6d30 /src/target/armv8.c | |
| parent | 5e0cc43838b898a125d7028ee1ec3c033c3b24c1 (diff) | |
| download | riscv-openocd-93f2276cdd99ad9e9d844150553621ea5d8524dd.zip riscv-openocd-93f2276cdd99ad9e9d844150553621ea5d8524dd.tar.gz riscv-openocd-93f2276cdd99ad9e9d844150553621ea5d8524dd.tar.bz2 | |
aarch64: support for aarch32 ARM_MODE_UND
Fix:
unrecognized psr mode: 0x1b
cannot read system control register in this mode: (UNRECOGNIZED : 0x1b)
Change-Id: I4dc3e72f90d57e52c0fe63cb59a7529a398757b3
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: Ifa5d21ae97492fde9e8c79ee7d99d8a2a871b1b5
Reviewed-on: https://review.openocd.org/c/openocd/+/6808
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src/target/armv8.c')
| -rw-r--r-- | src/target/armv8.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/target/armv8.c b/src/target/armv8.c index 26116bb..2de1157 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -78,6 +78,10 @@ static const struct { .psr = ARM_MODE_HYP, }, { + .name = "UND", + .psr = ARM_MODE_UND, + }, + { .name = "SYS", .psr = ARM_MODE_SYS, }, |