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| author | Tim Newsome <tim@sifive.com> | 2023-03-16 17:52:48 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2023-03-16 18:02:35 -0700 |
| commit | 868ebdd89ca75a73bffe335395aa1ed522dda660 (patch) | |
| tree | 95ead6f4982b85a6cc90d5832712523a8ee7b77a /src/target/armv7m.h | |
| parent | 3387015af01f18cc350c4764fbd533068ed15f3d (diff) | |
| parent | 1293ddd65713d6551775b67169387622ada477c1 (diff) | |
| download | riscv-openocd-868ebdd89ca75a73bffe335395aa1ed522dda660.zip riscv-openocd-868ebdd89ca75a73bffe335395aa1ed522dda660.tar.gz riscv-openocd-868ebdd89ca75a73bffe335395aa1ed522dda660.tar.bz2 | |
Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstream
This includes
https://sourceforge.net/p/openocd/mailman/message/37710818/, which
should fix #814.
Conflicts:
.travis.yml
contrib/loaders/flash/stm32/stm32f1x.S
contrib/loaders/flash/stm32/stm32f2x.S
doc/openocd.texi
src/rtos/FreeRTOS.c
src/server/gdb_server.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
src/target/riscv/riscv_semihosting.c
tcl/target/esp_common.cfg
tcl/target/gd32vf103.cfg
tools/scripts/checkpatch.pl
Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
Diffstat (limited to 'src/target/armv7m.h')
| -rw-r--r-- | src/target/armv7m.h | 28 |
1 files changed, 9 insertions, 19 deletions
diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 9ac121a..188bd56 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * @@ -7,19 +9,6 @@ * * * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program. If not, see <http://www.gnu.org/licenses/>. * ***************************************************************************/ #ifndef OPENOCD_TARGET_ARMV7M_H @@ -57,7 +46,7 @@ enum { ARMV7M_REGSEL_R14, ARMV7M_REGSEL_PC = 15, - ARMV7M_REGSEL_xPSR = 16, + ARMV7M_REGSEL_XPSR = 16, ARMV7M_REGSEL_MSP, ARMV7M_REGSEL_PSP, @@ -135,7 +124,7 @@ enum { ARMV7M_R14 = ARMV7M_REGSEL_R14, ARMV7M_PC = ARMV7M_REGSEL_PC, - ARMV7M_xPSR = ARMV7M_REGSEL_xPSR, + ARMV7M_XPSR = ARMV7M_REGSEL_XPSR, ARMV7M_MSP = ARMV7M_REGSEL_MSP, ARMV7M_PSP = ARMV7M_REGSEL_PSP, @@ -210,7 +199,7 @@ enum { /* for convenience add registers' block delimiters */ ARMV7M_LAST_REG, ARMV7M_CORE_FIRST_REG = ARMV7M_R0, - ARMV7M_CORE_LAST_REG = ARMV7M_xPSR, + ARMV7M_CORE_LAST_REG = ARMV7M_XPSR, ARMV7M_FPU_FIRST_REG = ARMV7M_D0, ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR, ARMV8M_FIRST_REG = ARMV8M_MSP_NS, @@ -226,12 +215,13 @@ enum { #define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1) -#define ARMV7M_COMMON_MAGIC 0x2A452A45 +#define ARMV7M_COMMON_MAGIC 0x2A452A45U struct armv7m_common { + unsigned int common_magic; + struct arm arm; - int common_magic; int exception_number; /* AP this processor is connected to in the DAP */ @@ -300,7 +290,7 @@ target_to_armv7m_safe(struct target *target) } struct armv7m_algorithm { - int common_magic; + unsigned int common_magic; enum arm_mode core_mode; |