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| author | Matthias Welwarsky <matthias@welwarsky.de> | 2015-10-18 13:50:58 +0200 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2015-11-30 05:43:03 +0000 |
| commit | f24aa404ba14bb048f55752b241a6a8185f77b3f (patch) | |
| tree | 25d94221865bd97d9e3d5640a91c74078bd2cffe /src/target/armv7a_cache.c | |
| parent | 9484dd5ebfcc7f9426f8ffc37f5486cd0387bb6a (diff) | |
| download | riscv-openocd-f24aa404ba14bb048f55752b241a6a8185f77b3f.zip riscv-openocd-f24aa404ba14bb048f55752b241a6a8185f77b3f.tar.gz riscv-openocd-f24aa404ba14bb048f55752b241a6a8185f77b3f.tar.bz2 | |
cortex_a: Update instruction cache after setting a soft breakpoint
Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint,
to make sure the d-cache is clean and invalid at the breakpoint
location down to PoC.
Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint
again, so that d-cache will pick up the modified code.
Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint
to memory to make the change visible to the CPU.
Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3033
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'src/target/armv7a_cache.c')
| -rw-r--r-- | src/target/armv7a_cache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c index a049174..acc388a 100644 --- a/src/target/armv7a_cache.c +++ b/src/target/armv7a_cache.c @@ -152,7 +152,7 @@ int armv7a_cache_auto_flush_all_data(struct target *target) } -static int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt, +int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt, uint32_t size) { struct armv7a_common *armv7a = target_to_armv7a(target); |