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| author | Oleksij Rempel <linux@rempel-privat.de> | 2015-04-23 07:49:13 +0200 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2015-11-30 05:39:40 +0000 |
| commit | cd440bd32a120a9b4c2d703d3d16dd52f16edab2 (patch) | |
| tree | 8c1ea72b9c50e10d3bab7e5f3d84415912ad3302 /src/target/armv7a.c | |
| parent | 74592a8435d0044bbf34a65765bca44166e61921 (diff) | |
| download | riscv-openocd-cd440bd32a120a9b4c2d703d3d16dd52f16edab2.zip riscv-openocd-cd440bd32a120a9b4c2d703d3d16dd52f16edab2.tar.gz riscv-openocd-cd440bd32a120a9b4c2d703d3d16dd52f16edab2.tar.bz2 | |
add armv7a_cache handlers
This patch introduces, new command set and handlers for l1 and l2x caches.
Patch set 10 folded the following changes into this one:
Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415
If8d87a03281d0f4ad402909998e7834eb4837e79
I0749f129fa74e04f4e9c20d143a744f09ef750d8
Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/2800
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'src/target/armv7a.c')
| -rw-r--r-- | src/target/armv7a.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/src/target/armv7a.c b/src/target/armv7a.c index de8a8cb..8219932 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -647,15 +647,28 @@ int armv7a_identify_cache(struct target *target) int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); struct arm_dpm *dpm = armv7a->arm.dpm; - uint32_t cache_selected, clidr; + uint32_t cache_selected, clidr, ctr; uint32_t cache_i_reg, cache_d_reg; struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache); if (!armv7a->is_armv7r) armv7a_read_ttbcr(target); retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + goto done; + /* retrieve CTR + * mrc p15, 0, r0, c0, c0, 1 @ read ctr */ + retval = dpm->instr_read_data_r0(dpm, + ARMV4_5_MRC(15, 0, 0, 0, 0, 1), + &ctr); if (retval != ERROR_OK) goto done; + + cache->iminline = 4UL << (ctr & 0xf); + cache->dminline = 4UL << ((ctr & 0xf0000) >> 16); + LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32, + ctr, cache->iminline, cache->dminline); + /* retrieve CLIDR * mrc p15, 1, r0, c0, c0, 1 @ read clidr */ retval = dpm->instr_read_data_r0(dpm, @@ -806,6 +819,7 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a) armv7a->armv7a_mmu.armv7a_cache.ctype = -1; armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL; armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL; + armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled = 1; return ERROR_OK; } @@ -869,7 +883,6 @@ const struct command_registration l2x_cache_command_handlers[] = { COMMAND_REGISTRATION_DONE }; - const struct command_registration armv7a_command_handlers[] = { { .chain = dap_command_handlers, @@ -877,5 +890,8 @@ const struct command_registration armv7a_command_handlers[] = { { .chain = l2x_cache_command_handlers, }, + { + .chain = arm7a_cache_command_handlers, + }, COMMAND_REGISTRATION_DONE }; |