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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2020-08-18 18:56:27 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-09-05 17:12:39 +0100 |
| commit | 99add6227fe0a3be536f9b83ff6aa7dd63a8d2dc (patch) | |
| tree | 03e6675ccaf3fbd8f86dfd9922a20574c8ca41cc /src/target/armv7a.c | |
| parent | e66593f8242d49dd05f6b9c4a5121fa466a158aa (diff) | |
| download | riscv-openocd-99add6227fe0a3be536f9b83ff6aa7dd63a8d2dc.zip riscv-openocd-99add6227fe0a3be536f9b83ff6aa7dd63a8d2dc.tar.gz riscv-openocd-99add6227fe0a3be536f9b83ff6aa7dd63a8d2dc.tar.bz2 | |
target: use proper format with uint32_t
Modify the format strings to properly handle uint32_t data types.
While there, fix prototype mismatch between header and C file of
the function armv7a_l1_d_cache_inval_virt().
Change-Id: I434bd241fa5c38e0c15d22cda2295097050067f5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5818
Tested-by: jenkins
Diffstat (limited to 'src/target/armv7a.c')
| -rw-r--r-- | src/target/armv7a.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 09dee91..c36744d 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -257,10 +257,10 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd, if (arch->ctype & 1) { command_print(cmd, - "L%d I-Cache: linelen %" PRIi32 - ", associativity %" PRIi32 - ", nsets %" PRIi32 - ", cachesize %" PRId32 " KBytes", + "L%d I-Cache: linelen %" PRIu32 + ", associativity %" PRIu32 + ", nsets %" PRIu32 + ", cachesize %" PRIu32 " KBytes", cl+1, arch->i_size.linelen, arch->i_size.associativity, @@ -270,10 +270,10 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd, if (arch->ctype >= 2) { command_print(cmd, - "L%d D-Cache: linelen %" PRIi32 - ", associativity %" PRIi32 - ", nsets %" PRIi32 - ", cachesize %" PRId32 " KBytes", + "L%d D-Cache: linelen %" PRIu32 + ", associativity %" PRIu32 + ", nsets %" PRIu32 + ", cachesize %" PRIu32 " KBytes", cl+1, arch->d_u_size.linelen, arch->d_u_size.associativity, @@ -283,7 +283,7 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd, } if (l2x_cache != NULL) - command_print(cmd, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways", + command_print(cmd, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRIu32 " ways", l2x_cache->base, l2x_cache->way); return ERROR_OK; @@ -399,7 +399,7 @@ int armv7a_identify_cache(struct target *target) cache->iminline = 4UL << (ctr & 0xf); cache->dminline = 4UL << ((ctr & 0xf0000) >> 16); - LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32, + LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32, ctr, cache->iminline, cache->dminline); /* retrieve CLIDR @@ -439,13 +439,13 @@ int armv7a_identify_cache(struct target *target) goto done; cache->arch[cl].d_u_size = decode_cache_reg(cache_reg); - LOG_DEBUG("data/unified cache index %d << %d, way %d << %d", + LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32, cache->arch[cl].d_u_size.index, cache->arch[cl].d_u_size.index_shift, cache->arch[cl].d_u_size.way, cache->arch[cl].d_u_size.way_shift); - LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways", + LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways", cache->arch[cl].d_u_size.linelen, cache->arch[cl].d_u_size.cachesize, cache->arch[cl].d_u_size.associativity); @@ -459,13 +459,13 @@ int armv7a_identify_cache(struct target *target) goto done; cache->arch[cl].i_size = decode_cache_reg(cache_reg); - LOG_DEBUG("instruction cache index %d << %d, way %d << %d", + LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32, cache->arch[cl].i_size.index, cache->arch[cl].i_size.index_shift, cache->arch[cl].i_size.way, cache->arch[cl].i_size.way_shift); - LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways", + LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways", cache->arch[cl].i_size.linelen, cache->arch[cl].i_size.cachesize, cache->arch[cl].i_size.associativity); |