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| author | Tommy Vestermark <tov@vestermark.dk> | 2019-04-11 20:40:36 +1000 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2019-04-24 14:10:13 +0100 |
| commit | 83515b60c9a506c458e614732165a791fa1a833a (patch) | |
| tree | 08dd8f6ac75a6906ef53b133e2f82543f068bdf8 /src/target/armv7a.c | |
| parent | 33281a87b66576057c14200e034e8e7e0a7e2d85 (diff) | |
| download | riscv-openocd-83515b60c9a506c458e614732165a791fa1a833a.zip riscv-openocd-83515b60c9a506c458e614732165a791fa1a833a.tar.gz riscv-openocd-83515b60c9a506c458e614732165a791fa1a833a.tar.bz2 | |
armv7a: Improve parsing of MPIDR register to avoid error message for Cortex R5
References:
- ARM DDI0406C ARMv7 Architecture Reference Manual, section B4.1.106
- ARM DDI0460D Cortex-R5 Technical Reference Manual section 4.3.6
- ARM 100048_0002_0 Cortex-A73 Technical Reference Manual section 4.5.2
Tested on: TMS570LC4357
Change-Id: Ie0d45fb697697f78cc4ad4e7a0116be9772590ba
Signed-off-by: Tommy Vestermark <tov@vestermark.dk>
Reviewed-on: http://openocd.zylin.com/5108
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/armv7a.c')
| -rw-r--r-- | src/target/armv7a.c | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 437a2f2..97ce473 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -307,23 +307,21 @@ static int armv7a_read_mpidr(struct target *target) if (retval != ERROR_OK) goto done; - /* ARMv7R uses a different format for MPIDR. - * When configured uniprocessor (most R cores) it reads as 0. - * This will need to be implemented for multiprocessor ARMv7R cores. */ - if (armv7a->is_armv7r) { - if (mpidr) - LOG_ERROR("MPIDR nonzero in ARMv7-R target"); - goto done; - } - - if (mpidr & 1<<31) { + /* Is register in Multiprocessing Extensions register format? */ + if (mpidr & MPIDR_MP_EXT) { + LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr); armv7a->multi_processor_system = (mpidr >> 30) & 1; + armv7a->multi_threading_processor = (mpidr >> 24) & 1; + armv7a->level2_id = (mpidr >> 16) & 0xf; armv7a->cluster_id = (mpidr >> 8) & 0xf; - armv7a->cpu_id = mpidr & 0x3; - LOG_INFO("%s cluster %x core %x %s", target_name(target), + armv7a->cpu_id = mpidr & 0xf; + LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s", + target_name(target), + armv7a->level2_id, armv7a->cluster_id, armv7a->cpu_id, - armv7a->multi_processor_system == 0 ? "multi core" : "mono core"); + armv7a->multi_processor_system == 0 ? "multi core" : "mono core", + armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT"); } else LOG_ERROR("MPIDR not in multiprocessor format"); |