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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2018-07-12 16:15:45 +0200 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-07-22 09:09:06 +0100 |
| commit | 42097baf19d4459a57f5224506e59a8347740f19 (patch) | |
| tree | 4a1baca9fbccae4c4203bb7c923936179eeb298a /src/target/armv7a.c | |
| parent | c584686fd1d1dc7d2059e619de90f35516598134 (diff) | |
| download | riscv-openocd-42097baf19d4459a57f5224506e59a8347740f19.zip riscv-openocd-42097baf19d4459a57f5224506e59a8347740f19.tar.gz riscv-openocd-42097baf19d4459a57f5224506e59a8347740f19.tar.bz2 | |
armv7a: read ttbcr and ttb0/1 at every entry in debug state
Commit bfc5c764df145f68835543119865eabe462e19c2 avoids reading
ttbcr and ttb0/1 at every virt2phys translation by caching them,
and it updates the cached values in armv7a_arch_state().
But the purpose of any (*arch_state)() method, thus including
armv7a_arch_state(), is to only print out and inform the user
about some architecture specific status.
Moreover, to reduce the verbosity during a GDB session, the
method (*arch_state)() is not executed anymore at debug state
entry (check use of target->verbose_halt_msg in src/openocd.c),
thus the state of translation table gets out-of-sync triggering
Error: Address translation failure
or even using a wrong address in the memory R/W operation.
In addition, the commit above breaks the case of armv7r by
calling armv7a_read_ttbcr() unconditionally.
Fixed by moving in cortex_a_post_debug_entry() the call to
armv7a_read_ttbcr() on armv7a case only.
Remove the call to armv7a_read_ttbcr() in armv7a_identify_cache()
since it is (conditionally) called only in the same procedure
cortex_a_post_debug_entry().
Fixes: bfc5c764df14 ("armv7a: cache ttbcr and ttb0/1 on debug
state entry")
Change-Id: Ifc20eca190111832e339a01b7f85d28c1547c8ba
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4601
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/armv7a.c')
| -rw-r--r-- | src/target/armv7a.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/target/armv7a.c b/src/target/armv7a.c index fab7363..eecfa70 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -124,7 +124,7 @@ done: return retval; } -static int armv7a_read_ttbcr(struct target *target) +int armv7a_read_ttbcr(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); struct arm_dpm *dpm = armv7a->arm.dpm; @@ -554,9 +554,6 @@ int armv7a_identify_cache(struct target *target) struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache); - if (!armv7a->is_armv7r) - armv7a_read_ttbcr(target); - retval = dpm->prepare(dpm); if (retval != ERROR_OK) goto done; @@ -729,8 +726,6 @@ int armv7a_arch_state(struct target *target) arm_arch_state(target); - armv7a_read_ttbcr(target); - if (armv7a->is_armv7r) { LOG_USER("D-Cache: %s, I-Cache: %s", state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], |