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| author | Evan Hunter <ehunter@broadcom.com> | 2012-10-12 09:45:33 +1100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-03-15 15:54:05 +0000 |
| commit | 13288a44bee0aa26067cb51c262b82a12b61699f (patch) | |
| tree | af838114f87e394c3caa6f91ae39bb6b45a2c0e8 /src/target/armv7a.c | |
| parent | 4e47519f6c519b792297efaa482852cd9eef554a (diff) | |
| download | riscv-openocd-13288a44bee0aa26067cb51c262b82a12b61699f.zip riscv-openocd-13288a44bee0aa26067cb51c262b82a12b61699f.tar.gz riscv-openocd-13288a44bee0aa26067cb51c262b82a12b61699f.tar.bz2 | |
arch: Added ARMv7R and Cortex-R4 support
Rewrite to merge Cortex-A and Cortex-R code
Change-Id: I4541557980d43d1bba6e8d1bfeb04f536ed25a00
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/358
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target/armv7a.c')
| -rw-r--r-- | src/target/armv7a.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 532b0b2..62a54b4 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -573,7 +573,8 @@ int armv7a_identify_cache(struct target *target) uint32_t cache_selected, clidr; uint32_t cache_i_reg, cache_d_reg; struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache); - armv7a_read_ttbcr(target); + if (!armv7a->is_armv7r) + armv7a_read_ttbcr(target); retval = dpm->prepare(dpm); if (retval != ERROR_OK) @@ -747,10 +748,16 @@ int armv7a_arch_state(struct target *target) arm_arch_state(target); - LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", - state[armv7a->armv7a_mmu.mmu_enabled], - state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], - state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); + if (armv7a->is_armv7r) { + LOG_USER("D-Cache: %s, I-Cache: %s", + state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], + state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); + } else { + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", + state[armv7a->armv7a_mmu.mmu_enabled], + state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], + state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); + } if (arm->core_mode == ARM_MODE_ABT) armv7a_show_fault_registers(target); |