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author | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-18 07:07:59 +0000 |
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committer | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-18 07:07:59 +0000 |
commit | f876d5e9c769a288faa7fd14b7bf373363542aab (patch) | |
tree | 86ad76530f7d44c69471813c4c727f107b018eb5 /src/target/arm_simulator.c | |
parent | c18947b947064e7eceed8047c42d4c8dfd8ae964 (diff) | |
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Transform 'u16' to 'uint16_t'
- Replace '\([^_]\)u16' with '\1uint16_t'.
- Replace '^u16' with 'uint16_t'.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2277 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/arm_simulator.c')
-rw-r--r-- | src/target/arm_simulator.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 186190b..163c87b 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -258,7 +258,7 @@ int pass_condition(u32 cpsr, u32 opcode) return 0; } -int thumb_pass_branch_condition(u32 cpsr, u16 opcode) +int thumb_pass_branch_condition(u32 cpsr, uint16_t opcode) { return pass_condition(cpsr, (opcode & 0x0f00) << 20); } @@ -307,7 +307,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) } else { - u16 opcode; + uint16_t opcode; if((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK) { |