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author | Omair Javaid <omair.javaid@linaro.org> | 2018-02-16 03:08:51 +0500 |
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committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-03-10 14:25:10 +0000 |
commit | f18ca510b3430a515f28f19ea6c6731a40022fb6 (patch) | |
tree | 0ca516cc31c369cabe071d31731b16a68188a215 /src/target/arm_opcodes.h | |
parent | 2830008be0f782f22e09f6ecd1764e168560de40 (diff) | |
download | riscv-openocd-f18ca510b3430a515f28f19ea6c6731a40022fb6.zip riscv-openocd-f18ca510b3430a515f28f19ea6c6731a40022fb6.tar.gz riscv-openocd-f18ca510b3430a515f28f19ea6c6731a40022fb6.tar.bz2 |
Support for Arm VFP v3 registers read/write
This patch adds support in openOCD to read/write Arm vector/floating
point registers. This is compatible with Arm vfp v3 target xml in GDB.
Please refer to binutils-gdb/gdb/features/arm/arm-vfpv3.xml
Change-Id: Id4dd1bddef51c558f1a86300c1a876d159463f18
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/4421
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
Diffstat (limited to 'src/target/arm_opcodes.h')
-rw-r--r-- | src/target/arm_opcodes.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h index a53fee7..482abe6 100644 --- a/src/target/arm_opcodes.h +++ b/src/target/arm_opcodes.h @@ -132,6 +132,30 @@ */ #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm)) +/* Copies two words from two ARM core registers + * into a doubleword extension register, or + * from a doubleword extension register to two ARM core registers. + * See Armv7-A arch reference manual section A8.8.345 + * Rt: Arm core register 1 + * Rt2: Arm core register 2 + * Vm: The doubleword extension register + * M: m = UInt(M:Vm); + * op: to_arm_registers = (op == ‘1’); + */ +#define ARMV4_5_VMOV(op, Rt2, Rt, M, Vm) \ + (0xec400b10 | ((op) << 20) | ((Rt2) << 16) | \ + ((Rt) << 12) | ((M) << 5) | (Vm)) + +/* Moves the value of the FPSCR to an ARM core register + * Rt: Arm core register + */ +#define ARMV4_5_VMRS(Rt) (0xeef10a10 | ((Rt) << 12)) + +/* Moves the value of an ARM core register to the FPSCR. + * Rt: Arm core register + */ +#define ARMV4_5_VMSR(Rt) (0xeee10a10 | ((Rt) << 12)) + /* Store data from coprocessor to consecutive memory * See Armv7-A arch doc section A8.6.187 * P: 1=index mode (offset from Rn) |