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| author | Tomas Vanek <vanekt@fbl.cz> | 2023-04-02 17:23:46 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2024-01-06 13:56:43 +0000 |
| commit | adcc8ef87bc1ed47c95f1f2d23072b2b916e1555 (patch) | |
| tree | 9e9558b7b46ca15a0c1ce79b35ee1b3b52424842 /src/target/arm_adi_v5.h | |
| parent | ffdcec938fb6bd2d6f7f1f4aed7b41c627934a24 (diff) | |
| download | riscv-openocd-adcc8ef87bc1ed47c95f1f2d23072b2b916e1555.zip riscv-openocd-adcc8ef87bc1ed47c95f1f2d23072b2b916e1555.tar.gz riscv-openocd-adcc8ef87bc1ed47c95f1f2d23072b2b916e1555.tar.bz2 | |
target/adiv5: probe MEM-AP supported transfer sizes including large data
Based on Daniel Goehring's [1] and Peter Collingbourne's [2] work.
Probe for support of 8, 16 bit and if the large data extension is available
also probe for 64, 128 and 256 bit operations.
Probe for the ability of packing 8 and 16 bit data
(formerly probed in mem_ap_init()). The probe is integrated to
mem_ap_read/write() routines and takes place just before the first memory
access of the specific size.
Add 64, 128 and 256 bit MEM-AP read/writes.
Introduce specific error codes for unsupported transfer size
and for unsupported packing.
Change-Id: I180c4ef17d2fc3189e8e2f14bafd22d857f29608
Link: 7191: target/adiv5: add MEM-AP 64-bit access support | https://review.openocd.org/c/openocd/+/7191
Link: 7436: arm_adi_v5: Support reads wider than 32 bits | https://review.openocd.org/c/openocd/+/7436
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7576
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'src/target/arm_adi_v5.h')
| -rw-r--r-- | src/target/arm_adi_v5.h | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index fc7fdaf..60c161f 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -165,6 +165,9 @@ #define CSW_8BIT 0 #define CSW_16BIT 1 #define CSW_32BIT 2 +#define CSW_64BIT 3 +#define CSW_128BIT 4 +#define CSW_256BIT 5 #define CSW_ADDRINC_MASK (3UL << 4) #define CSW_ADDRINC_OFF 0UL #define CSW_ADDRINC_SINGLE (1UL << 4) @@ -270,6 +273,26 @@ struct adiv5_ap { uint32_t csw_value; /** + * Save the supported CSW.Size data types for the MEM-AP. + * Each bit corresponds to a data type. + * 0b1 = Supported data size. 0b0 = Not supported. + * Bit 0 = Byte (8-bits) + * Bit 1 = Halfword (16-bits) + * Bit 2 = Word (32-bits) - always supported by spec. + * Bit 3 = Doubleword (64-bits) + * Bit 4 = 128-bits + * Bit 5 = 256-bits + */ + uint32_t csw_size_supported_mask; + /** + * Probed CSW.Size data types for the MEM-AP. + * Each bit corresponds to a data type. + * 0b1 = Data size has been probed. 0b0 = Not yet probed. + * Bits assigned to sizes same way as above. + */ + uint32_t csw_size_probed_mask; + + /** * Cache for (MEM-AP) AP_REG_TAR register value This is written to * configure the address being read or written * "-1" indicates no cached value. @@ -286,7 +309,8 @@ struct adiv5_ap { uint32_t tar_autoincr_block; /* true if packed transfers are supported by the MEM-AP */ - bool packed_transfers; + bool packed_transfers_supported; + bool packed_transfers_probed; /* true if unaligned memory access is not supported by the MEM-AP */ bool unaligned_access_bad; |