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| author | Leonard Crestez <leonard.crestez@nxp.com> | 2019-04-16 22:12:18 +0300 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2019-05-25 21:50:30 +0100 |
| commit | 2288394b4568d978ac63c66dc4dc163f7117e5c5 (patch) | |
| tree | d6857762909aa12a4652fe2a95e8aec923da8707 /src/target/arm_adi_v5.h | |
| parent | 51ef02a5d161820f6d0be8f7984c3dc057b395a9 (diff) | |
| download | riscv-openocd-2288394b4568d978ac63c66dc4dc163f7117e5c5.zip riscv-openocd-2288394b4568d978ac63c66dc4dc163f7117e5c5.tar.gz riscv-openocd-2288394b4568d978ac63c66dc4dc163f7117e5c5.tar.bz2 | |
arm_adi_v5: Split CSW bits into AHB/APB/AXI
The implementation-defined bits have different semantics for each bus
and different recommended defaults.
Change-Id: I562fe24643bb1f3abc696339e382a75ccf2f2873
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-on: http://openocd.zylin.com/5124
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'src/target/arm_adi_v5.h')
| -rw-r--r-- | src/target/arm_adi_v5.h | 31 |
1 files changed, 25 insertions, 6 deletions
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 0b61b75..50fd359 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -112,15 +112,34 @@ #define CSW_ADDRINC_PACKED (2UL << 4) #define CSW_DEVICE_EN (1UL << 6) #define CSW_TRIN_PROG (1UL << 7) -/* all fields in bits 12 and above are implementation-defined! */ + +/* All fields in bits 12 and above are implementation-defined + * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI + * Some bits are shared between buses + */ #define CSW_SPIDEN (1UL << 23) -#define CSW_HPROT1 (1UL << 25) /* AHB: Privileged */ -#define CSW_MASTER_DEBUG (1UL << 29) /* AHB: set HMASTER signals to AHB-AP ID */ -#define CSW_SPROT (1UL << 30) #define CSW_DBGSWENABLE (1UL << 31) -/* initial value of csw_default used for MEM-AP transfers */ -#define CSW_DEFAULT (CSW_HPROT1 | CSW_MASTER_DEBUG | CSW_DBGSWENABLE) +/* AHB: Privileged */ +#define CSW_AHB_HPROT1 (1UL << 25) +/* AHB: set HMASTER signals to AHB-AP ID */ +#define CSW_AHB_MASTER_DEBUG (1UL << 29) +/* AHB5: non-secure access via HNONSEC + * AHB3: SBO, UNPREDICTABLE if zero */ +#define CSW_AHB_SPROT (1UL << 30) +/* AHB: initial value of csw_default */ +#define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE) + +/* AXI: Privileged */ +#define CSW_AXI_ARPROT0_PRIV (1UL << 28) +/* AXI: Non-secure */ +#define CSW_AXI_ARPROT1_NONSEC (1UL << 29) +/* AXI: initial value of csw_default */ +#define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE) + +/* APB: initial value of csw_default */ +#define CSW_APB_DEFAULT (CSW_DBGSWENABLE) + /* Fields of the MEM-AP's IDR register */ #define IDR_REV (0xFUL << 28) |