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| author | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2016-02-22 23:15:52 +0100 |
|---|---|---|
| committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2016-05-17 21:52:30 +0100 |
| commit | 150b7d26f213398d717bf46744811b48834a3744 (patch) | |
| tree | ffc64ea1eecf05cd26f6b17dca1d26c3ce26f672 /src/target/arm_adi_v5.h | |
| parent | 56a889f4d46125f8a322d0ca468774b6a5703f97 (diff) | |
| download | riscv-openocd-150b7d26f213398d717bf46744811b48834a3744.zip riscv-openocd-150b7d26f213398d717bf46744811b48834a3744.tar.gz riscv-openocd-150b7d26f213398d717bf46744811b48834a3744.tar.bz2 | |
arm_adi_v5: Update DP (Debug Port) registers defined in ADIv5.2.
Note:
WCR (Wire Control Register) is replaced by DLCR (Data Link Control
Register). And only TURNROUND field is modifiable.
[andreas.fritiofson@gmail.com]:
Rename DP_IDCODE to DP_DPIDR as well.
Sort list by address and align it using spaces instead of tabs. Add
comments about supporting DP versions.
Remove non-functional wcr command completely.
Change-Id: Ic6b781b07c8eead8b0237d497846d0da060cb1ba
Signed-off-by: Alamy Liu <alamy.liu@gmail.com>
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3244
Tested-by: jenkins
Diffstat (limited to 'src/target/arm_adi_v5.h')
| -rw-r--r-- | src/target/arm_adi_v5.h | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 7c27d60..13ced9f 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -47,18 +47,21 @@ /* A[3:0] for DP registers; A[1:0] are always zero. * - JTAG accesses all of these via JTAG_DP_DPACC, except for * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT). - * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL + * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL */ -#define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */ -#define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */ -#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */ -#define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */ -#define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */ -#define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */ -#define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */ - -#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */ -#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */ +#define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */ +#define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */ +#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */ +#define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */ +#define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */ +#define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */ +#define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */ +#define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */ +#define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */ +#define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */ +#define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */ + +#define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */ /* Fields of the DP's AP ABORT register */ #define DAPABORT (1UL << 0) |