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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2021-08-05 17:08:11 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-08-14 13:30:35 +0100 |
| commit | 020e46d1868a0b936a4e5b53c4d75706bb524618 (patch) | |
| tree | 2d9b2ca62e5d23bb81f75356a7d9674daf71c01e /src/target/arm_adi_v5.h | |
| parent | 2f97856c5b3097199c23ddbfe53a98d25895b500 (diff) | |
| download | riscv-openocd-020e46d1868a0b936a4e5b53c4d75706bb524618.zip riscv-openocd-020e46d1868a0b936a4e5b53c4d75706bb524618.tar.gz riscv-openocd-020e46d1868a0b936a4e5b53c4d75706bb524618.tar.bz2 | |
arm_adi_v5: fix access to 64-bit MEM-AP
Commit ac22cdc57322 ("target/adiv5: Large Physical Address
Extension") reads the register MEM_AP_REG_CFG and keeps it in a
new field of struct adiv5_ap. The test on LE bit (Large Extension)
is used to identify if mem_ap addresses are 32 or 64 bits.
But the register MEM_AP_REG_CFG is only read during mem_ap_init(),
that is called only when the AP is used as a target debug AP or if
a target mem_ap is attached to that AP.
The openocd commands '<dapname> baseaddr', '<dapname> info' and
'dap info' can be executed on AP that has not been associated yet
to a target, thus executed without any knowledge of MEM_AP_REG_CFG
value. The initialization to ADI_BAD_CFG causes openocd to always
use 32 bit mode on un-associated APs.
Verify if MEM_AP_REG_CFG has not been read and eventually read it.
In case of 32 bits mode AP, MEM_AP_REG_BASE64 is defined as 'RES0'
(reserved, but readable); the code can queue both the read of
MEM_AP_REG_CFG and MEM_AP_REG_BASE64, before knowing if the former
is required. This speeds-up the operation.
Rename ADI_BAD_CFG as MEM_AP_REG_CFG_INVALID.
Change-Id: If3bbd792b56a483022c37ccc2ce82b5ba5c36caa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: ac22cdc57322 ("target/adiv5: Large Physical Address Extension")
Reviewed-on: http://openocd.zylin.com/6412
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Diffstat (limited to 'src/target/arm_adi_v5.h')
| -rw-r--r-- | src/target/arm_adi_v5.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 5d1e793..73ceea0 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -151,9 +151,10 @@ #define CSW_APB_DEFAULT (CSW_DBGSWENABLE) /* Fields of the MEM-AP's CFG register */ -#define MEM_AP_REG_CFG_BE BIT(0) -#define MEM_AP_REG_CFG_LA BIT(1) -#define MEM_AP_REG_CFG_LD BIT(2) +#define MEM_AP_REG_CFG_BE BIT(0) +#define MEM_AP_REG_CFG_LA BIT(1) +#define MEM_AP_REG_CFG_LD BIT(2) +#define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8 /* Fields of the MEM-AP's IDR register */ #define IDR_REV (0xFUL << 28) |