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| author | Linus Walleij <linus.walleij@linaro.org> | 2016-01-12 10:46:07 +0100 |
|---|---|---|
| committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2016-02-29 20:14:12 +0000 |
| commit | fed713104904bfc4884e748ef4160be4ab7e4575 (patch) | |
| tree | 9ee698ef7669bf12e48f5952979e7a36dda1f714 /src/target/arm.h | |
| parent | f2fbcb217b31e1b133ac18f51f7fc4ab3cf386b1 (diff) | |
| download | riscv-openocd-fed713104904bfc4884e748ef4160be4ab7e4575.zip riscv-openocd-fed713104904bfc4884e748ef4160be4ab7e4575.tar.gz riscv-openocd-fed713104904bfc4884e748ef4160be4ab7e4575.tar.bz2 | |
armv4_5: support weirdo ARMv6 secure monitor mode
On the ARM PB1176JZF-S the system comes up in secure monitor
mode after reset. However the modebits in CPSR form the value
28 (0x1c) and CPSR is 0x800001dc deeming it UNRECOGNIZED.
Define this mode to be synonymous to mode 22 (MON) and things
start to work like a charm.
Change-Id: I001f7773ee1076202c0c633e466d2d833f7a1413
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-on: http://openocd.zylin.com/3196
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'src/target/arm.h')
| -rw-r--r-- | src/target/arm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/target/arm.h b/src/target/arm.h index 27636cc..d8361bd 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -61,6 +61,7 @@ enum arm_mode { ARM_MODE_MON = 22, ARM_MODE_ABT = 23, ARM_MODE_UND = 27, + ARM_MODE_1176_MON = 28, ARM_MODE_SYS = 31, ARM_MODE_THREAD = 0, |