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| author | Omair Javaid <omair.javaid@linaro.org> | 2018-02-16 03:08:51 +0500 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-03-10 14:25:10 +0000 |
| commit | f18ca510b3430a515f28f19ea6c6731a40022fb6 (patch) | |
| tree | 0ca516cc31c369cabe071d31731b16a68188a215 /src/target/arm.h | |
| parent | 2830008be0f782f22e09f6ecd1764e168560de40 (diff) | |
| download | riscv-openocd-f18ca510b3430a515f28f19ea6c6731a40022fb6.zip riscv-openocd-f18ca510b3430a515f28f19ea6c6731a40022fb6.tar.gz riscv-openocd-f18ca510b3430a515f28f19ea6c6731a40022fb6.tar.bz2 | |
Support for Arm VFP v3 registers read/write
This patch adds support in openOCD to read/write Arm vector/floating
point registers. This is compatible with Arm vfp v3 target xml in GDB.
Please refer to binutils-gdb/gdb/features/arm/arm-vfpv3.xml
Change-Id: Id4dd1bddef51c558f1a86300c1a876d159463f18
Signed-off-by: Omair Javaid <omair.javaid@linaro.org>
Reviewed-on: http://openocd.zylin.com/4421
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Tested-by: jenkins
Diffstat (limited to 'src/target/arm.h')
| -rw-r--r-- | src/target/arm.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/target/arm.h b/src/target/arm.h index c7963dd..62fbb73 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -77,6 +77,43 @@ enum arm_mode { ARM_MODE_ANY = -1 }; +/* VFPv3 internal register numbers mapping to d0:31 */ +enum { + ARM_VFP_V3_D0 = 51, + ARM_VFP_V3_D1, + ARM_VFP_V3_D2, + ARM_VFP_V3_D3, + ARM_VFP_V3_D4, + ARM_VFP_V3_D5, + ARM_VFP_V3_D6, + ARM_VFP_V3_D7, + ARM_VFP_V3_D8, + ARM_VFP_V3_D9, + ARM_VFP_V3_D10, + ARM_VFP_V3_D11, + ARM_VFP_V3_D12, + ARM_VFP_V3_D13, + ARM_VFP_V3_D14, + ARM_VFP_V3_D15, + ARM_VFP_V3_D16, + ARM_VFP_V3_D17, + ARM_VFP_V3_D18, + ARM_VFP_V3_D19, + ARM_VFP_V3_D20, + ARM_VFP_V3_D21, + ARM_VFP_V3_D22, + ARM_VFP_V3_D23, + ARM_VFP_V3_D24, + ARM_VFP_V3_D25, + ARM_VFP_V3_D26, + ARM_VFP_V3_D27, + ARM_VFP_V3_D28, + ARM_VFP_V3_D29, + ARM_VFP_V3_D30, + ARM_VFP_V3_D31, + ARM_VFP_V3_FPSCR, +}; + const char *arm_mode_name(unsigned psr_mode); bool is_arm_mode(unsigned psr_mode); @@ -89,6 +126,14 @@ enum arm_state { ARM_STATE_AARCH64, }; +/** ARM vector floating point enabled, if yes which version. */ +enum arm_vfp_version { + ARM_VFP_DISABLED, + ARM_VFP_V1, + ARM_VFP_V2, + ARM_VFP_V3, +}; + #define ARM_COMMON_MAGIC 0x0A450A45 /** @@ -145,6 +190,9 @@ struct arm { /** Flag reporting whether semihosting fileio operation is active. */ bool semihosting_hit_fileio; + /** Floating point or VFP version, 0 if disabled. */ + int arm_vfp_version; + /** Current semihosting operation. */ int semihosting_op; |