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author | David Brownell <dbrownell@users.sourceforge.net> | 2010-02-21 14:34:33 -0800 |
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committer | David Brownell <dbrownell@users.sourceforge.net> | 2010-02-21 14:34:33 -0800 |
commit | 1aac72d24339380f6e98c50dec4c96ab30537749 (patch) | |
tree | efd8b83082f072d807f168eabf415e1002cf5425 /src/target/arm.h | |
parent | a299371a9ec109da3851cb43aed3e9157d095358 (diff) | |
download | riscv-openocd-1aac72d24339380f6e98c50dec4c96ab30537749.zip riscv-openocd-1aac72d24339380f6e98c50dec4c96ab30537749.tar.gz riscv-openocd-1aac72d24339380f6e98c50dec4c96ab30537749.tar.bz2 |
ARM: keep a handle to the PC
Keep a handle to the PC in "struct arm", and use it.
This register is used a fair amount, so this is a net
minor code shrink (other than some line length fixes),
but mostly it's to make things more readable.
For XScale, fix a dodgy sequence while stepping. It
was initializing a variable to a non-NULL value, then
updating it to handle the step-over-active-breakpoint
case, and then later testing for non-NULL to see if
it should reverse that step-over-active logic. It
should have done like ARM7/ARM9 does: init to NULL.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm.h')
-rw-r--r-- | src/target/arm.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/target/arm.h b/src/target/arm.h index c72b194..6b304e9 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -95,6 +95,9 @@ struct arm { int common_magic; struct reg_cache *core_cache; + /** Handle to the PC; valid in all core modes. */ + struct reg *pc; + /** Handle to the CPSR; valid in all core modes. */ struct reg *cpsr; |