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author | Evgeniy Didin <didin@synopsys.com> | 2020-05-15 23:04:01 +0300 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-06-27 15:34:24 +0100 |
commit | 057aed11a2f80645322ff76c7dd0c7908582d0a4 (patch) | |
tree | 1dbf0f12ea59e53d4c3dfe25c6700448ac6722e5 /src/target/arc_mem.c | |
parent | 2e6904eef5e81e71453168ed8c6f649e3a5c0f6c (diff) | |
download | riscv-openocd-057aed11a2f80645322ff76c7dd0c7908582d0a4.zip riscv-openocd-057aed11a2f80645322ff76c7dd0c7908582d0a4.tar.gz riscv-openocd-057aed11a2f80645322ff76c7dd0c7908582d0a4.tar.bz2 |
target/arc: Introduce L1I,L1D,L2 caches support
With this commit we introduce L1 and L2 cache
flush and invalidate operations which are necessary for
getting/setting actual data during memory r/w operations.
We introduce L2 cache support, which is not presented
on currently support EMSK board. But L2 is presented
on HSDK board, which soon will be introduced.
Change-Id: I2fda505a47ecb8833cc9f5ffe24f6a4e22ab6eb0
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5688
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src/target/arc_mem.c')
-rw-r--r-- | src/target/arc_mem.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/target/arc_mem.c b/src/target/arc_mem.c index e80bfb4..866c71f 100644 --- a/src/target/arc_mem.c +++ b/src/target/arc_mem.c @@ -41,10 +41,18 @@ static int arc_mem_write_block32(struct target *target, uint32_t addr, /* Check arguments */ assert(!(addr & 3)); + /* We need to flush the cache since it might contain dirty + * lines, so the cache invalidation may cause data inconsistency. */ + CHECK_RETVAL(arc_cache_flush(target)); + + /* No need to flush cache, because we don't read values from memory. */ CHECK_RETVAL(arc_jtag_write_memory(&arc->jtag_info, addr, count, (uint32_t *)buf)); + /* Invalidate caches. */ + CHECK_RETVAL(arc_cache_invalidate(target)); + return ERROR_OK; } @@ -64,6 +72,9 @@ static int arc_mem_write_block16(struct target *target, uint32_t addr, /* Check arguments */ assert(!(addr & 1)); + /* We will read data from memory, so we need to flush the cache. */ + CHECK_RETVAL(arc_cache_flush(target)); + /* non-word writes are less common, than 4-byte writes, so I suppose we can * allowe ourselves to write this in a cycle, instead of calling arc_jtag * with count > 1. */ @@ -97,6 +108,9 @@ static int arc_mem_write_block16(struct target *target, uint32_t addr, (addr + i * sizeof(uint16_t)) & ~3u, 1, &buffer_he)); } + /* Invalidate caches. */ + CHECK_RETVAL(arc_cache_invalidate(target)); + return ERROR_OK; } @@ -113,6 +127,9 @@ static int arc_mem_write_block8(struct target *target, uint32_t addr, LOG_DEBUG("Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32, addr, count); + /* We will read data from memory, so we need to flush the cache. */ + CHECK_RETVAL(arc_cache_flush(target)); + /* non-word writes are less common, than 4-byte writes, so I suppose we can * allowe ourselves to write this in a cycle, instead of calling arc_jtag * with count > 1. */ @@ -128,6 +145,9 @@ static int arc_mem_write_block8(struct target *target, uint32_t addr, CHECK_RETVAL(arc_jtag_write_memory(&arc->jtag_info, (addr + i) & ~3, 1, &buffer_he)); } + /* Invalidate caches. */ + CHECK_RETVAL(arc_cache_invalidate(target)); + return ERROR_OK; } @@ -205,6 +225,9 @@ static int arc_mem_read_block(struct target *target, target_addr_t addr, assert(!(addr & 3)); assert(size == 4); + /* Flush cache before memory access */ + CHECK_RETVAL(arc_cache_flush(target)); + CHECK_RETVAL(arc_jtag_read_memory(&arc->jtag_info, addr, count, buf, arc_mem_is_slow_memory(arc, addr, size, count))); |