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| author | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-04-16 16:49:29 +0300 |
|---|---|---|
| committer | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-06-04 19:22:11 +0300 |
| commit | cb87885c0067840962b65d7ebb86de6949cb5967 (patch) | |
| tree | 17605e3d7d328e104932d37a9b29dd6e7de092d9 /src/target/algorithm.c | |
| parent | c470cd21ae3b2e76551ec73782d48bc4520e7145 (diff) | |
| download | riscv-openocd-cb87885c0067840962b65d7ebb86de6949cb5967.zip riscv-openocd-cb87885c0067840962b65d7ebb86de6949cb5967.tar.gz riscv-openocd-cb87885c0067840962b65d7ebb86de6949cb5967.tar.bz2 | |
target/riscv: stop using register_get/set for 0.11 targets
Caching is somewhat handled in `riscv-011.c`. Handling it additionaly in
`riscv.c` may cause problems. Sice there is no simulator that supports
RISC-V Debug Specification v0.11, so it is not feaseable to automate
testing.
This commit separates 0.11 register accesses and unlocks further
development in this area.
Change-Id: I73ff17ef85106c4ababa38319f446f6c384a1750
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Diffstat (limited to 'src/target/algorithm.c')
0 files changed, 0 insertions, 0 deletions