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| author | Kevin Burke <kevinb@os.amperecomputing.com> | 2021-02-09 17:27:03 -0500 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-07-02 17:12:11 +0100 |
| commit | ac22cdc573225fa5860f25821eed52d92ea633e7 (patch) | |
| tree | 31d1a9787af22e7ab40a03737a892fe8817cfcbb /src/target/aarch64.c | |
| parent | 920cacd74c4cd9c54d20c5c0738d8d28a456fdf1 (diff) | |
| download | riscv-openocd-ac22cdc573225fa5860f25821eed52d92ea633e7.zip riscv-openocd-ac22cdc573225fa5860f25821eed52d92ea633e7.tar.gz riscv-openocd-ac22cdc573225fa5860f25821eed52d92ea633e7.tar.bz2 | |
target/adiv5: Large Physical Address Extension
Provides ARM LPAE support to allow 64-bit TAR setting
on MEM AP accesses.
Tested on a 4-core ARM ARES Processor system using an
AXI Access Port.
Change-Id: I88f7a0a57a6abb58665032929194a41dd8729f6b
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: http://openocd.zylin.com/5576
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src/target/aarch64.c')
| -rw-r--r-- | src/target/aarch64.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 171c286..d43ade1 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -252,7 +252,7 @@ static int aarch64_init_debug_access(struct target *target) /* Write to memory mapped registers directly with no cache or mmu handling */ static int aarch64_dap_write_memap_register_u32(struct target *target, - uint32_t address, + target_addr_t address, uint32_t value) { int retval; @@ -2571,7 +2571,7 @@ static int aarch64_examine_first(struct target *target) armv8->debug_ap->memaccess_tck = 10; if (!target->dbgbase_set) { - uint32_t dbgbase; + target_addr_t dbgbase; /* Get ROM Table base */ uint32_t apid; int32_t coreidx = target->coreid; @@ -2583,7 +2583,7 @@ static int aarch64_examine_first(struct target *target) &armv8->debug_base, &coreidx); if (retval != ERROR_OK) return retval; - LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32 + LOG_DEBUG("Detected core %" PRId32 " dbgbase: " TARGET_ADDR_FMT " apid: %08" PRIx32, coreidx, armv8->debug_base, apid); } else armv8->debug_base = target->dbgbase; |