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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2020-08-18 18:56:27 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-09-05 17:12:39 +0100 |
| commit | 99add6227fe0a3be536f9b83ff6aa7dd63a8d2dc (patch) | |
| tree | 03e6675ccaf3fbd8f86dfd9922a20574c8ca41cc /src/target/aarch64.c | |
| parent | e66593f8242d49dd05f6b9c4a5121fa466a158aa (diff) | |
| download | riscv-openocd-99add6227fe0a3be536f9b83ff6aa7dd63a8d2dc.zip riscv-openocd-99add6227fe0a3be536f9b83ff6aa7dd63a8d2dc.tar.gz riscv-openocd-99add6227fe0a3be536f9b83ff6aa7dd63a8d2dc.tar.bz2 | |
target: use proper format with uint32_t
Modify the format strings to properly handle uint32_t data types.
While there, fix prototype mismatch between header and C file of
the function armv7a_l1_d_cache_inval_virt().
Change-Id: I434bd241fa5c38e0c15d22cda2295097050067f5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5818
Tested-by: jenkins
Diffstat (limited to 'src/target/aarch64.c')
| -rw-r--r-- | src/target/aarch64.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c index e6b1cc0..4febc8c 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -105,7 +105,7 @@ static int aarch64_restore_system_control_reg(struct target *target) break; default: - LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")", + LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)", armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode); return ERROR_FAIL; } @@ -180,7 +180,7 @@ static int aarch64_mmu_modify(struct target *target, int enable) break; default: - LOG_DEBUG("unknown cpu state 0x%" PRIx32, armv8->arm.core_mode); + LOG_DEBUG("unknown cpu state 0x%x", armv8->arm.core_mode); break; } @@ -1042,7 +1042,7 @@ static int aarch64_post_debug_entry(struct target *target) break; default: - LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")", + LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)", armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode); return ERROR_FAIL; } |