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| author | Tim Newsome <tim@sifive.com> | 2020-03-26 09:08:56 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-26 09:08:56 -0700 |
| commit | 5b2426a4b2c3d0eb244bb8ec276ef24228e9e31d (patch) | |
| tree | 187bc82c115b244bfee14ba6d7d2880616651b40 /src/server | |
| parent | 548790fefc5da04a2a60d6fb54f765c7bf959e42 (diff) | |
| download | riscv-openocd-5b2426a4b2c3d0eb244bb8ec276ef24228e9e31d.zip riscv-openocd-5b2426a4b2c3d0eb244bb8ec276ef24228e9e31d.tar.gz riscv-openocd-5b2426a4b2c3d0eb244bb8ec276ef24228e9e31d.tar.bz2 | |
Deal with vlenb being unreadable. (#458)
Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.
Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
Diffstat (limited to 'src/server')
0 files changed, 0 insertions, 0 deletions