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authorSteven Stallion <stallion@squareup.com>2018-08-28 17:18:01 -0700
committerMatthias Welwarsky <matthias@welwarsky.de>2018-10-16 11:58:24 +0100
commit4ab75a3634901c4e3897d771e2c75a64c7353c28 (patch)
tree475731fa20dae25c39a88804e894b69c69900e2f /src/rtos/uCOS-III.c
parente72b2601e71f49af10f72c4bb6220ee2061ef173 (diff)
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esirisc: support eSi-RISC targets
eSi-RISC is a highly configurable microprocessor architecture for embedded systems provided by EnSilica. This patch adds support for 32-bit targets and also includes an internal flash driver and uC/OS-III RTOS support. This is a non-traditional target and required a number of additional changes to support non-linear register numbers and the 'p' packet in RTOS support for proper integration into EnSilica's GDB port. Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/4660 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/rtos/uCOS-III.c')
-rw-r--r--src/rtos/uCOS-III.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/rtos/uCOS-III.c b/src/rtos/uCOS-III.c
index e06bf41..3cd9c2a 100644
--- a/src/rtos/uCOS-III.c
+++ b/src/rtos/uCOS-III.c
@@ -68,6 +68,20 @@ static const struct uCOS_III_params uCOS_III_params_list[] = {
&rtos_uCOS_III_Cortex_M_stacking, /* stacking_info */
0, /* num_threads */
},
+ {
+ "esirisc", /* target_name */
+ sizeof(uint32_t), /* pointer_width */
+ 0, /* thread_stack_offset */
+ 0, /* thread_name_offset */
+ 0, /* thread_state_offset */
+ 0, /* thread_priority_offset */
+ 0, /* thread_prev_offset */
+ 0, /* thread_next_offset */
+ false, /* thread_offsets_updated */
+ 1, /* threadid_start */
+ &rtos_uCOS_III_eSi_RISC_stacking, /* stacking_info */
+ 0, /* num_threads */
+ },
};
static const char * const uCOS_III_symbol_list[] = {