rtos: support gdb_get_register_packet

This patch adds support for p packet responses by targets configured
with RTOS support. This change required moving to a rtos_reg struct,
which is similar to struct reg used by targets, which resulted in
needing to update each stacking with register numbers. This patch also
allows targets with non-linear register numbers to function with RTOSes
as well.

Change-Id: I5b189d74110d6b6f2fa851a67ab0762ae6b1832f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4121
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

1 files changed, 113 insertions, 113 deletions

diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c
index 931cfc7..7b054cb 100644
--- a/src/rtos/rtos_standard_stackings.c
+++ b/src/rtos/rtos_standard_stackings.c
@@ -24,132 +24,132 @@
 #include "target/armv7m.h"
 
 static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
-	{ 0x20, 32 },		/* r0   */
-	{ 0x24, 32 },		/* r1   */
-	{ 0x28, 32 },		/* r2   */
-	{ 0x2c, 32 },		/* r3   */
-	{ 0x00, 32 },		/* r4   */
-	{ 0x04, 32 },		/* r5   */
-	{ 0x08, 32 },		/* r6   */
-	{ 0x0c, 32 },		/* r7   */
-	{ 0x10, 32 },		/* r8   */
-	{ 0x14, 32 },		/* r9   */
-	{ 0x18, 32 },		/* r10  */
-	{ 0x1c, 32 },		/* r11  */
-	{ 0x30, 32 },		/* r12  */
-	{ -2,   32 },		/* sp   */
-	{ 0x34, 32 },		/* lr   */
-	{ 0x38, 32 },		/* pc   */
-	{ 0x3c, 32 },		/* xPSR */
+	{ ARMV7M_R0,   0x20, 32 },		/* r0   */
+	{ ARMV7M_R1,   0x24, 32 },		/* r1   */
+	{ ARMV7M_R2,   0x28, 32 },		/* r2   */
+	{ ARMV7M_R3,   0x2c, 32 },		/* r3   */
+	{ ARMV7M_R4,   0x00, 32 },		/* r4   */
+	{ ARMV7M_R5,   0x04, 32 },		/* r5   */
+	{ ARMV7M_R6,   0x08, 32 },		/* r6   */
+	{ ARMV7M_R7,   0x0c, 32 },		/* r7   */
+	{ ARMV7M_R8,   0x10, 32 },		/* r8   */
+	{ ARMV7M_R9,   0x14, 32 },		/* r9   */
+	{ ARMV7M_R10,  0x18, 32 },		/* r10  */
+	{ ARMV7M_R11,  0x1c, 32 },		/* r11  */
+	{ ARMV7M_R12,  0x30, 32 },		/* r12  */
+	{ ARMV7M_R13,  -2,   32 },		/* sp   */
+	{ ARMV7M_R14,  0x34, 32 },		/* lr   */
+	{ ARMV7M_PC,   0x38, 32 },		/* pc   */
+	{ ARMV7M_xPSR, 0x3c, 32 },		/* xPSR */
 };
 
 static const struct stack_register_offset rtos_standard_Cortex_M4F_stack_offsets[] = {
-	{ 0x24, 32 },		/* r0   */
-	{ 0x28, 32 },		/* r1   */
-	{ 0x2c, 32 },		/* r2   */
-	{ 0x30, 32 },		/* r3   */
-	{ 0x00, 32 },		/* r4   */
-	{ 0x04, 32 },		/* r5   */
-	{ 0x08, 32 },		/* r6   */
-	{ 0x0c, 32 },		/* r7   */
-	{ 0x10, 32 },		/* r8   */
-	{ 0x14, 32 },		/* r9   */
-	{ 0x18, 32 },		/* r10  */
-	{ 0x1c, 32 },		/* r11  */
-	{ 0x34, 32 },		/* r12  */
-	{ -2,   32 },		/* sp   */
-	{ 0x38, 32 },		/* lr   */
-	{ 0x3c, 32 },		/* pc   */
-	{ 0x40, 32 },		/* xPSR */
+	{ ARMV7M_R0,   0x24, 32 },		/* r0   */
+	{ ARMV7M_R1,   0x28, 32 },		/* r1   */
+	{ ARMV7M_R2,   0x2c, 32 },		/* r2   */
+	{ ARMV7M_R3,   0x30, 32 },		/* r3   */
+	{ ARMV7M_R4,   0x00, 32 },		/* r4   */
+	{ ARMV7M_R5,   0x04, 32 },		/* r5   */
+	{ ARMV7M_R6,   0x08, 32 },		/* r6   */
+	{ ARMV7M_R7,   0x0c, 32 },		/* r7   */
+	{ ARMV7M_R8,   0x10, 32 },		/* r8   */
+	{ ARMV7M_R9,   0x14, 32 },		/* r9   */
+	{ ARMV7M_R10,  0x18, 32 },		/* r10  */
+	{ ARMV7M_R11,  0x1c, 32 },		/* r11  */
+	{ ARMV7M_R12,  0x34, 32 },		/* r12  */
+	{ ARMV7M_R13,  -2,   32 },		/* sp   */
+	{ ARMV7M_R14,  0x38, 32 },		/* lr   */
+	{ ARMV7M_PC,   0x3c, 32 },		/* pc   */
+	{ ARMV7M_xPSR, 0x40, 32 },		/* xPSR */
 };
 
 static const struct stack_register_offset rtos_standard_Cortex_M4F_FPU_stack_offsets[] = {
-	{ 0x64, 32 },		/* r0   */
-	{ 0x68, 32 },		/* r1   */
-	{ 0x6c, 32 },		/* r2   */
-	{ 0x70, 32 },		/* r3   */
-	{ 0x00, 32 },		/* r4   */
-	{ 0x04, 32 },		/* r5   */
-	{ 0x08, 32 },		/* r6   */
-	{ 0x0c, 32 },		/* r7   */
-	{ 0x10, 32 },		/* r8   */
-	{ 0x14, 32 },		/* r9   */
-	{ 0x18, 32 },		/* r10  */
-	{ 0x1c, 32 },		/* r11  */
-	{ 0x74, 32 },		/* r12  */
-	{ -2,   32 },		/* sp   */
-	{ 0x78, 32 },		/* lr   */
-	{ 0x7c, 32 },		/* pc   */
-	{ 0x80, 32 },		/* xPSR */
+	{ ARMV7M_R0,   0x64, 32 },		/* r0   */
+	{ ARMV7M_R1,   0x68, 32 },		/* r1   */
+	{ ARMV7M_R2,   0x6c, 32 },		/* r2   */
+	{ ARMV7M_R3,   0x70, 32 },		/* r3   */
+	{ ARMV7M_R4,   0x00, 32 },		/* r4   */
+	{ ARMV7M_R5,   0x04, 32 },		/* r5   */
+	{ ARMV7M_R6,   0x08, 32 },		/* r6   */
+	{ ARMV7M_R7,   0x0c, 32 },		/* r7   */
+	{ ARMV7M_R8,   0x10, 32 },		/* r8   */
+	{ ARMV7M_R9,   0x14, 32 },		/* r9   */
+	{ ARMV7M_R10,  0x18, 32 },		/* r10  */
+	{ ARMV7M_R11,  0x1c, 32 },		/* r11  */
+	{ ARMV7M_R12,  0x74, 32 },		/* r12  */
+	{ ARMV7M_R13,  -2,   32 },		/* sp   */
+	{ ARMV7M_R14,  0x78, 32 },		/* lr   */
+	{ ARMV7M_PC,   0x7c, 32 },		/* pc   */
+	{ ARMV7M_xPSR, 0x80, 32 },		/* xPSR */
 };
 
 
 static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = {
-	{ 0x08, 32 },		/* r0  (a1)   */
-	{ 0x0c, 32 },		/* r1  (a2)  */
-	{ 0x10, 32 },		/* r2  (a3)  */
-	{ 0x14, 32 },		/* r3  (a4)  */
-	{ 0x18, 32 },		/* r4  (v1)  */
-	{ 0x1c, 32 },		/* r5  (v2)  */
-	{ 0x20, 32 },		/* r6  (v3)  */
-	{ 0x24, 32 },		/* r7  (v4)  */
-	{ 0x28, 32 },		/* r8  (a1)  */
-	{ 0x2c, 32 },		/* r9  (sb)  */
-	{ 0x30, 32 },		/* r10 (sl) */
-	{ 0x34, 32 },		/* r11 (fp) */
-	{ 0x38, 32 },		/* r12 (ip) */
-	{ -2,   32 },		/* sp   */
-	{ 0x3c, 32 },		/* lr   */
-	{ 0x40, 32 },		/* pc   */
-	{ -1,   96 },		/* FPA1 */
-	{ -1,   96 },		/* FPA2 */
-	{ -1,   96 },		/* FPA3 */
-	{ -1,   96 },		/* FPA4 */
-	{ -1,   96 },		/* FPA5 */
-	{ -1,   96 },		/* FPA6 */
-	{ -1,   96 },		/* FPA7 */
-	{ -1,   96 },		/* FPA8 */
-	{ -1,   32 },		/* FPS  */
-	{ 0x04, 32 },		/* CSPR */
+	{ 0,  0x08, 32 },		/* r0  (a1)   */
+	{ 1,  0x0c, 32 },		/* r1  (a2)  */
+	{ 2,  0x10, 32 },		/* r2  (a3)  */
+	{ 3,  0x14, 32 },		/* r3  (a4)  */
+	{ 4,  0x18, 32 },		/* r4  (v1)  */
+	{ 5,  0x1c, 32 },		/* r5  (v2)  */
+	{ 6,  0x20, 32 },		/* r6  (v3)  */
+	{ 7,  0x24, 32 },		/* r7  (v4)  */
+	{ 8,  0x28, 32 },		/* r8  (a1)  */
+	{ 10, 0x2c, 32 },		/* r9  (sb)  */
+	{ 11, 0x30, 32 },		/* r10 (sl) */
+	{ 12, 0x34, 32 },		/* r11 (fp) */
+	{ 13, 0x38, 32 },		/* r12 (ip) */
+	{ 14, -2,   32 },		/* sp   */
+	{ 15, 0x3c, 32 },		/* lr   */
+	{ 16, 0x40, 32 },		/* pc   */
+	{ 17, -1,   96 },		/* FPA1 */
+	{ 18, -1,   96 },		/* FPA2 */
+	{ 19, -1,   96 },		/* FPA3 */
+	{ 20, -1,   96 },		/* FPA4 */
+	{ 21, -1,   96 },		/* FPA5 */
+	{ 22, -1,   96 },		/* FPA6 */
+	{ 23, -1,   96 },		/* FPA7 */
+	{ 24, -1,   96 },		/* FPA8 */
+	{ 25, -1,   32 },		/* FPS  */
+	{ 26, 0x04, 32 },		/* CSPR */
 };
 
 static const struct stack_register_offset rtos_standard_NDS32_N1068_stack_offsets[] = {
-	{ 0x88, 32 },		/* R0  */
-	{ 0x8C, 32 },		/* R1 */
-	{ 0x14, 32 },		/* R2 */
-	{ 0x18, 32 },		/* R3 */
-	{ 0x1C, 32 },		/* R4 */
-	{ 0x20, 32 },		/* R5 */
-	{ 0x24, 32 },		/* R6 */
-	{ 0x28, 32 },		/* R7 */
-	{ 0x2C, 32 },		/* R8 */
-	{ 0x30, 32 },		/* R9 */
-	{ 0x34, 32 },		/* R10 */
-	{ 0x38, 32 },		/* R11 */
-	{ 0x3C, 32 },		/* R12 */
-	{ 0x40, 32 },		/* R13 */
-	{ 0x44, 32 },		/* R14 */
-	{ 0x48, 32 },		/* R15 */
-	{ 0x4C, 32 },		/* R16 */
-	{ 0x50, 32 },		/* R17 */
-	{ 0x54, 32 },		/* R18 */
-	{ 0x58, 32 },		/* R19 */
-	{ 0x5C, 32 },		/* R20 */
-	{ 0x60, 32 },		/* R21 */
-	{ 0x64, 32 },		/* R22 */
-	{ 0x68, 32 },		/* R23 */
-	{ 0x6C, 32 },		/* R24 */
-	{ 0x70, 32 },		/* R25 */
-	{ 0x74, 32 },		/* R26 */
-	{ 0x78, 32 },		/* R27 */
-	{ 0x7C, 32 },		/* R28 */
-	{ 0x80, 32 },		/* R29 */
-	{ 0x84, 32 },		/* R30 (LP) */
-	{ 0x00, 32 },		/* R31 (SP) */
-	{ 0x04, 32 },		/* PSW */
-	{ 0x08, 32 },		/* IPC */
-	{ 0x0C, 32 },		/* IPSW */
-	{ 0x10, 32 },		/* IFC_LP */
+	{ 0,  0x88, 32 },		/* R0  */
+	{ 1,  0x8C, 32 },		/* R1 */
+	{ 2,  0x14, 32 },		/* R2 */
+	{ 3,  0x18, 32 },		/* R3 */
+	{ 4,  0x1C, 32 },		/* R4 */
+	{ 5,  0x20, 32 },		/* R5 */
+	{ 6,  0x24, 32 },		/* R6 */
+	{ 7,  0x28, 32 },		/* R7 */
+	{ 8,  0x2C, 32 },		/* R8 */
+	{ 9,  0x30, 32 },		/* R9 */
+	{ 10, 0x34, 32 },		/* R10 */
+	{ 11, 0x38, 32 },		/* R11 */
+	{ 12, 0x3C, 32 },		/* R12 */
+	{ 13, 0x40, 32 },		/* R13 */
+	{ 14, 0x44, 32 },		/* R14 */
+	{ 15, 0x48, 32 },		/* R15 */
+	{ 16, 0x4C, 32 },		/* R16 */
+	{ 17, 0x50, 32 },		/* R17 */
+	{ 18, 0x54, 32 },		/* R18 */
+	{ 19, 0x58, 32 },		/* R19 */
+	{ 20, 0x5C, 32 },		/* R20 */
+	{ 21, 0x60, 32 },		/* R21 */
+	{ 22, 0x64, 32 },		/* R22 */
+	{ 23, 0x68, 32 },		/* R23 */
+	{ 24, 0x6C, 32 },		/* R24 */
+	{ 25, 0x70, 32 },		/* R25 */
+	{ 26, 0x74, 32 },		/* R26 */
+	{ 27, 0x78, 32 },		/* R27 */
+	{ 28, 0x7C, 32 },		/* R28 */
+	{ 29, 0x80, 32 },		/* R29 */
+	{ 30, 0x84, 32 },		/* R30 (LP) */
+	{ 31, 0x00, 32 },		/* R31 (SP) */
+	{ 32, 0x04, 32 },		/* PSW */
+	{ 33, 0x08, 32 },		/* IPC */
+	{ 34, 0x0C, 32 },		/* IPSW */
+	{ 35, 0x10, 32 },		/* IFC_LP */
 };
 
 static int64_t rtos_generic_stack_align(struct target *target,