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| author | Evgeniy Naydanov <109669442+en-sc@users.noreply.github.com> | 2024-06-10 12:01:18 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-10 12:01:18 +0300 |
| commit | 38ec813ad852a4e6f029a9d4f6da4eaf5e5f1e5e (patch) | |
| tree | 227b11a2bd346c321a74a627c18c7c2d5496de45 /src/pld/intel.c | |
| parent | 568baf8c0bbf87fd8d6f5bd7ffaad59f1cd9ebea (diff) | |
| parent | 9555b741b1d17c8a2dabb40a2d86d1db00671679 (diff) | |
| download | riscv-openocd-38ec813ad852a4e6f029a9d4f6da4eaf5e5f1e5e.zip riscv-openocd-38ec813ad852a4e6f029a9d4f6da4eaf5e5f1e5e.tar.gz riscv-openocd-38ec813ad852a4e6f029a9d4f6da4eaf5e5f1e5e.tar.bz2 | |
Merge pull request #1073 from en-sc/en-sc/abs-reg-batch
target/riscv: write registers using batch
Diffstat (limited to 'src/pld/intel.c')
0 files changed, 0 insertions, 0 deletions