diff options
| author | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-04-26 11:36:25 +0300 |
|---|---|---|
| committer | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-05-15 18:58:47 +0300 |
| commit | 418fcf1ceac981973eb898a03a3ea8136bc3db9c (patch) | |
| tree | b60a15d94c7ffabf44f3ce00fc6694cec91b5063 /src/jtag | |
| parent | 16db1b77ffbb8d615b3b39cbaedf2b78bce8d967 (diff) | |
| download | riscv-openocd-418fcf1ceac981973eb898a03a3ea8136bc3db9c.zip riscv-openocd-418fcf1ceac981973eb898a03a3ea8136bc3db9c.tar.gz riscv-openocd-418fcf1ceac981973eb898a03a3ea8136bc3db9c.tar.bz2 | |
target/riscv: only `dmactive` can be written if `dmactive` is low
There was an error introduced by
8319eee9e1ffc601b94b4223958180b49f8b8188.
According to RISC-V Debug Spec 1.0.0-rc1 [3.14.2. Debug Module Contro]:
> 0 (inactive): The module’s state, including authentication mechanism,
takes its reset values (the dmactive bit is the only bit which can be
written to something other than its reset value).
`dmactive` was written together with `hartsel` and `hasel` in
8319eee9e1ffc601b94b4223958180b49f8b8188.
Change-Id: I11fba35cb87f8261c0a4a45e28b2813a5a086078
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Diffstat (limited to 'src/jtag')
0 files changed, 0 insertions, 0 deletions