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| author | Raúl Sanchez Siles <rasasi78@gmail.com> | 2021-03-13 01:09:01 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2021-03-16 08:51:37 +0000 |
| commit | 8d6f7c92239a54ce77d7a268f51b49445470fe00 (patch) | |
| tree | bbf5e8a495e7889320e08e0140cbdbbcfc869444 /src/jtag/swim.h | |
| parent | 4c00f96fc2e32397da5b46ca3428a992333548da (diff) | |
| download | riscv-openocd-8d6f7c92239a54ce77d7a268f51b49445470fe00.zip riscv-openocd-8d6f7c92239a54ce77d7a268f51b49445470fe00.tar.gz riscv-openocd-8d6f7c92239a54ce77d7a268f51b49445470fe00.tar.bz2 | |
flash/stm32l4x: zero init stm32l4_flash_bank struct on flash bank initialization
This is specially needed when, in the probe routine, device is not
found among the stm32l4_parts. In this case, the stm32l4_flash_bank->part_info
is undefined and inadvertentanly used afterwards:
part_info = stm32l4_info->part_info;
If the stm32l4_flash_bank is zero init, the probe routine checks for
the validity of the part_info field in the previous struct and correctly
detects the unsupported (or not found) condition, raising an error
rather than a SIGSEGV
Change-Id: I7d9d669fb3fa7f8f0903acd60046966b4acb0031
Signed-off-by: Raúl Sánchez Siles <rasasi78@gmail.com>
Reviewed-on: http://openocd.zylin.com/6103
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'src/jtag/swim.h')
0 files changed, 0 insertions, 0 deletions