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author | Tomas Vanek <vanekt@fbl.cz> | 2021-11-12 09:49:01 +0100 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-11-20 14:44:54 +0000 |
commit | 872682345af6e26af145c76d5a4373b16d815b7e (patch) | |
tree | 2e260d09820182c35bf8eefb328257e2352da079 /src/jtag/swd.h | |
parent | 3eef83e4bd2b112b98d73f8b0947af93c193e0ef (diff) | |
download | riscv-openocd-872682345af6e26af145c76d5a4373b16d815b7e.zip riscv-openocd-872682345af6e26af145c76d5a4373b16d815b7e.tar.gz riscv-openocd-872682345af6e26af145c76d5a4373b16d815b7e.tar.bz2 |
drivers/swd: add support for SWD multidrop
According to ARM IHI0031C+ chapter 2.3.11 "TARGETSEL, Target Selection register"
multidrop capable DPv2 must not drive SWDIO line during the response phase
of a write to TARGETSEL register.
Introduce helper functions swd_cmd_returns_ack() and swd_ack_to_error_code()
to centralize these tests from all drivers to one place.
Introduce distinct error codes for SWD protocol.
Partly inspired by Graham Sanderson's http://review.openocd.org/4935
Change-Id: Ie5f9edb22e066a933a534bf2b29e7e1d3087dad1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6699
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'src/jtag/swd.h')
-rw-r--r-- | src/jtag/swd.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/jtag/swd.h b/src/jtag/swd.h index fe28667..8a436d0 100644 --- a/src/jtag/swd.h +++ b/src/jtag/swd.h @@ -18,6 +18,7 @@ #ifndef OPENOCD_JTAG_SWD_H #define OPENOCD_JTAG_SWD_H +#include <helper/log.h> #include <target/arm_adi_v5.h> /* Bits in SWD command packets, written from host to target @@ -32,6 +33,12 @@ #define SWD_CMD_PARK (1 << 7) /* driven high by host */ /* followed by TRN, 3-bits of ACK, TRN */ +/* + * The SWD subsystem error codes + */ +#define ERROR_SWD_FAIL (-400) /** protocol or parity error */ +#define ERROR_SWD_FAULT (-401) /** device returned FAULT in ACK field */ + /** * Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg() * and swd_driver.write_reg() methods will use directly. @@ -53,6 +60,40 @@ static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum) /* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */ +/** + * Test if we can rely on ACK returned by SWD command + * + * @param cmd Byte constructed by swd_cmd(), START, STOP and TRN are filtered off + * @returns true if ACK should be checked, false if should be ignored + */ +static inline bool swd_cmd_returns_ack(uint8_t cmd) +{ + uint8_t base_cmd = cmd & (SWD_CMD_APNDP | SWD_CMD_RNW | SWD_CMD_A32); + + /* DPv2 does not reply to DP_TARGETSEL write cmd */ + return base_cmd != swd_cmd(false, false, DP_TARGETSEL); +} + +/** + * Convert SWD ACK value returned from DP to OpenOCD error code + * + * @param ack + * @returns error code + */ +static inline int swd_ack_to_error_code(uint8_t ack) +{ + switch (ack) { + case SWD_ACK_OK: + return ERROR_OK; + case SWD_ACK_WAIT: + return ERROR_WAIT; + case SWD_ACK_FAULT: + return ERROR_SWD_FAULT; + default: + return ERROR_SWD_FAIL; + } +} + /* * The following sequences are updated to * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E |