aboutsummaryrefslogtreecommitdiff
path: root/src/flash/nand
diff options
context:
space:
mode:
authorTomas Vanek <vanekt@fbl.cz>2021-11-25 06:24:52 +0100
committerTomas Vanek <vanekt@fbl.cz>2022-02-25 20:28:02 +0000
commit13cd75b6ecfd8d9cf04e56b182b6a162ad50247c (patch)
treef7bf9ce7a2e1b552ba66701f22704ccceca6bb45 /src/flash/nand
parentb53f5c257185e5410622ed72790affb1bda88248 (diff)
downloadriscv-openocd-13cd75b6ecfd8d9cf04e56b182b6a162ad50247c.zip
riscv-openocd-13cd75b6ecfd8d9cf04e56b182b6a162ad50247c.tar.gz
riscv-openocd-13cd75b6ecfd8d9cf04e56b182b6a162ad50247c.tar.bz2
flash/nor/stm32xx: fix segfault accessing Cortex-M part number
Some of STM32 flash drivers read Cortex-M part number from cortex_m->core_info. In corner cases the core_info pointer was observed uninitialised even if target_was_examined() returned true. See also [1] Use the new and safe helper to get Cortex-M part number. While on it switch also target_to_cm()/target_to_armv7m() to the safe versions. This prevents a crash when the flash bank is misconfigured with non-Cortex-M target. Add missing checks for target_was_examined() to flash probes. [1] 6545: fix crash in case cortex_m->core_info is not set https://review.openocd.org/c/openocd/+/6545 Change-Id: If2471af74ebfe22f14442f48ae109b2e1bb5fa3b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Fixes: f5898bd93ff8 (flash/stm32fxx.c: do not read CPUID as this info is stored in cortex_m_common) Reviewed-on: https://review.openocd.org/c/openocd/+/6752 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Diffstat (limited to 'src/flash/nand')
0 files changed, 0 insertions, 0 deletions