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authorJacek Wuwer <jacekmw8@gmail.com>2022-05-04 10:15:57 +0200
committerAntonio Borneo <borneo.antonio@gmail.com>2022-07-30 08:48:21 +0000
commitf97915f248d7e3e7db49139b4fbb40e1e480ed53 (patch)
tree7040667082811af116a529834dd98a49ac413f86 /doc
parent49cf334e98dc2e6f52d64e594b8067247841b37d (diff)
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drivers/vdebug: add support for DAP level interface
This patch adds support for DAP interface to Cadence vdebug driver. It implements a new transport layer for dapdirect_swd. Change-Id: I64b02a9e1ce91e552e07fca692879655496f88b6 Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6965 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi4
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index b213798..03bb508 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -594,8 +594,8 @@ produced, PDF schematics are easily found and it is easy to make.
@item @b{vdebug}
@* A driver for Cadence virtual Debug Interface to emulated or simulated targets.
It implements a client connecting to the vdebug server, which in turn communicates
-with the emulated or simulated RTL model through a transactor. The current version
-supports only JTAG as a transport, but other virtual transports, like DAP are planned.
+with the emulated or simulated RTL model through a transactor. The driver supports
+JTAG and DAP-level transports.
@item @b{jtag_dpi}
@* A JTAG driver acting as a client for the SystemVerilog Direct Programming