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| author | Esben Haabendal <esben@haabendal.dk> | 2015-11-10 11:44:29 +0100 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2016-06-23 07:37:36 +0100 |
| commit | f906c65fed5f3f2df54c6aaf2ea28d9742d44db4 (patch) | |
| tree | 67f4b97645f2e43625e65880f9d736357e2b50fe /doc | |
| parent | 406f4d1c68330e3bf8d9db4e402fd8802a5c79e2 (diff) | |
| download | riscv-openocd-f906c65fed5f3f2df54c6aaf2ea28d9742d44db4.zip riscv-openocd-f906c65fed5f3f2df54c6aaf2ea28d9742d44db4.tar.gz riscv-openocd-f906c65fed5f3f2df54c6aaf2ea28d9742d44db4.tar.bz2 | |
Support for Freescale LS102x SAP
The SAP in LS102x SoC's from Freescale is able to read and write to all
physical memory locations, independently of CPU cores and DAP.
This implementation is 100% based on reverse-engineering of JTAG
communication with an LS1021A SAP using a JTAG debugger with SAP support.
And as such, this code is for now "works-for-me", pending verification
by other OpenOCD users, or even better, actual information from Freescale
on the SAP interface.
Change-Id: Ibb30945e017894da5c402f9f633fc513bed4e68c
Signed-off-by: Esben Haabendal <esben@haabendal.dk>
Reviewed-on: http://openocd.zylin.com/3096
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index ae92697..30a2a46 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4059,6 +4059,8 @@ compact Thumb2 instruction set. not a CPU type. It is based on the ARMv5 architecture. @item @code{openrisc} -- this is an OpenRISC 1000 core. The current implementation supports three JTAG TAP cores: +@item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs, +allowing access to physical memory addresses independently of CPU cores. @itemize @minus @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag}) @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf}) |