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| author | Tomas Vanek <vanekt@fbl.cz> | 2021-11-16 12:23:48 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2022-04-24 08:26:08 +0000 |
| commit | f2b4897773a1c9db185dfb61d474055559fd507a (patch) | |
| tree | 6793b031e3173502fca50d4b3619ceaab3af51d8 /doc | |
| parent | a26ee5344cf70e068265ac2f03a2915fae070e14 (diff) | |
| download | riscv-openocd-f2b4897773a1c9db185dfb61d474055559fd507a.zip riscv-openocd-f2b4897773a1c9db185dfb61d474055559fd507a.tar.gz riscv-openocd-f2b4897773a1c9db185dfb61d474055559fd507a.tar.bz2 | |
flash/stm32f1x: add support for RISC-V GigaDevice GD32VF103
The device has compatible flash macro with STM32F1 family, reuse
stm32f1x driver code.
Detect non-ARM target - for simplicy test target type name 'riscv'
and the address has 32 bits.
In case of RISC-V CPU use simple chunked write algo - async algo
cannot be used as the core implemented in this device doesn't
allow memory access while running.
Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6704
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 1218735..d550027 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -7293,6 +7293,7 @@ applied to all of them. All members of the STM32F0, STM32F1 and STM32F3 microcontroller families from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores. +The driver also works with GD32VF103 powered by RISC-V core. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. |