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author | Daniel Anselmi <danselmi@gmx.ch> | 2022-12-12 09:49:51 +0100 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-04-30 14:54:38 +0000 |
commit | db0609aeb4d5c8dec607afb1e07f5083d3b242c3 (patch) | |
tree | c391f7b7cea74cd31410ebf44905078e1575b900 /doc | |
parent | 7c6d44644082eb33d91af62091c37ba1384555ad (diff) | |
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pld: add support for altera/intel devices
Change-Id: I7977d39c9037ae71139f78c8d381f5f925dc3489
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7355
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'doc')
-rw-r--r-- | doc/openocd.texi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 6037b8b..8099455 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -8530,6 +8530,34 @@ This driver can be used to load the bitstream into the FPGA. @end deffn +@deffn {FPGA Driver} {intel} [@option{family}] +This driver can be used to load the bitstream into Intel (former Altera) FPGAs. +The families Cyclone III, Cyclone IV, Cyclone V, Cyclone 10, Arria II are supported. +@c Arria V and Arria 10, MAX II, MAX V, MAX10) + +The option @option{family} is one of @var{cycloneiii cycloneiv cyclonev cyclone10 arriaii}. +This is needed when the JTAG ID of the device is ambiguous (same ID is used for chips in different families). + +As input file format the driver supports a '.rbf' (raw bitstream file) file. The '.rbf' file can be generated +from a '.sof' file with @verb{|quartus_cpf -c blinker.sof blinker.rbf|} + +Defines a new PLD device, an FPGA of the Cyclone III family, using the TAP named @verb{|cycloneiii.tap|}: +@example +pld device intel cycloneiii.tap cycloneiii +@end example + +@deffn {Command} {intel set_bscan} num len +Set boundary scan register length of FPGA @var{num} to @var{len}. This is needed because the +length can vary between chips with the same JTAG ID. +@end deffn + +@deffn {Command} {intel set_check_pos} num pos +Selects the position @var{pos} in the boundary-scan register. The bit at this +position is checked after loading the bitstream and must be '1', which is the case when no error occurred. +With a value of -1 for @var{pos} the check will be omitted. +@end deffn +@end deffn + @node General Commands @chapter General Commands |