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authorTarek BOCHKATI <tarek.bouchkati@gmail.com>2020-03-02 13:58:07 +0100
committerOleksij Rempel <linux@rempel-privat.de>2020-03-27 07:11:45 +0000
commitaf69f5ad0bb0cd38ad3163a8a3f3602d751c5d6d (patch)
treeec1dad47763b5b651adbc7eceec6e7c041126eba /doc
parentf00070edaf8fbe7e49c44845c440086d55288f28 (diff)
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doc: fix OpenRISC target documentation
OpenRISC correct target name is 'or1k' not 'openrisc' http://openocd.zylin.com/3096 introduced a conflict between 'openrisc' and 'ls1_sap' documentations Change-Id: Iedebbf9809300e1272334c5b63d0b31a41062282 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5485 Tested-by: jenkins Reviewed-by: Esben Haabendal <esbenhaabendal@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi4
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index e60d269..b5692e6 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4434,10 +4434,10 @@ The current implementation supports eSi-32xx cores.
@item @code{mips_m4k} -- a MIPS core
@item @code{xscale} -- this is actually an architecture,
not a CPU type. It is based on the ARMv5 architecture.
-@item @code{openrisc} -- this is an OpenRISC 1000 core.
-The current implementation supports three JTAG TAP cores:
@item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
allowing access to physical memory addresses independently of CPU cores.
+@item @code{or1k} -- this is an OpenRISC 1000 core.
+The current implementation supports three JTAG TAP cores:
@itemize @minus
@item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
@item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})