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| author | Tim Newsome <tim@sifive.com> | 2022-05-03 13:41:55 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-05-03 13:41:55 -0700 |
| commit | 9460f43dc356829858bcb0057c7fe0dd7153c0c6 (patch) | |
| tree | 51fa5e6f157caeffeec27d0dba117c01389f6d66 /doc | |
| parent | b6dddfacc05ea981aabcf76ed155f68b677950a1 (diff) | |
| parent | 66335683fec62ac89da48d64932fd9d082314225 (diff) | |
| download | riscv-openocd-9460f43dc356829858bcb0057c7fe0dd7153c0c6.zip riscv-openocd-9460f43dc356829858bcb0057c7fe0dd7153c0c6.tar.gz riscv-openocd-9460f43dc356829858bcb0057c7fe0dd7153c0c6.tar.bz2 | |
Merge branch 'master' into from_upstream
Conflicts:
tcl/target/gd32vf103.cfg
I kept our version, except I changed the flash device as happened in
mainline. Once this file settles down in mainline, we can copy it
wholesale into this fork.
Change-Id: I4c5b21fec0734b5e08eba392883e006a46386b1c
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 1870287..ac7ad88 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4728,9 +4728,9 @@ specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will be emulated to comply to GDB remote protocol. @item @code{mips_m4k} -- a MIPS core. @item @code{mips_mips64} -- a MIPS64 core. -@item @code{nds32_v2} -- this is an Andes NDS32 v2 core. -@item @code{nds32_v3} -- this is an Andes NDS32 v3 core. -@item @code{nds32_v3m} -- this is an Andes NDS32 v3m core. +@item @code{nds32_v2} -- this is an Andes NDS32 v2 core (deprecated; would be removed in v0.13.0). +@item @code{nds32_v3} -- this is an Andes NDS32 v3 core (deprecated; would be removed in v0.13.0). +@item @code{nds32_v3m} -- this is an Andes NDS32 v3m core (deprecated; would be removed in v0.13.0). @item @code{or1k} -- this is an OpenRISC 1000 core. The current implementation supports three JTAG TAP cores: @itemize @minus @@ -7293,6 +7293,7 @@ applied to all of them. All members of the STM32F0, STM32F1 and STM32F3 microcontroller families from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores. +The driver also works with GD32VF103 powered by RISC-V core. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. |