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| author | Sergio Chico <sergio.chico@gmail.com> | 2013-11-10 16:03:40 +0100 |
|---|---|---|
| committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2013-12-14 21:53:16 +0000 |
| commit | 93a3a82e49e7d1df855095dd541e9c04ad7823bc (patch) | |
| tree | a26d5939605b3c86bb3407bf683da241eb55757f /doc | |
| parent | 2d64cf92aed12fc785afe8bd8bd759ae28a6b2eb (diff) | |
| download | riscv-openocd-93a3a82e49e7d1df855095dd541e9c04ad7823bc.zip riscv-openocd-93a3a82e49e7d1df855095dd541e9c04ad7823bc.tar.gz riscv-openocd-93a3a82e49e7d1df855095dd541e9c04ad7823bc.tar.bz2 | |
topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc
This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.
Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188
Signed-off-by: Sergio Chico <sergio.chico@gmail.com>
Reviewed-on: http://openocd.zylin.com/1806
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index aa0bb5d..5f2b89e 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4181,10 +4181,11 @@ There are several variants defined: @item @code{pxa3xx} ... instruction register length is 11 bits @end itemize @item @code{openrisc} -- this is an OpenRISC 1000 core. -The current implementation supports two JTAG TAP cores: +The current implementation supports three JTAG TAP cores: @itemize @minus @item @code{OpenCores TAP} (See: @emph{http://opencores.org/project,jtag}) @item @code{Altera Virtual JTAG TAP} (See: @emph{http://www.altera.com/literature/ug/ug_virtualjtag.pdf}) +@item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @emph{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf}) @end itemize And two debug interfaces cores: @itemize @minus @@ -7517,8 +7518,8 @@ The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be configured with any of the TAP / Debug Unit available. @subsection TAP and Debug Unit selection commands -@deffn Command {tap_select} (@option{vjtag}|@option{mohor}) -Select between the Altera Virtual JTAG and Mohor TAP. +@deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan}) +Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP. @end deffn @deffn Command {du_select} (@option{adv}|@option{mohor}) [option] Select between the Advanced Debug Interface and the classic one. |