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authorTim Newsome <tim@sifive.com>2023-11-20 12:30:19 -0800
committerTim Newsome <tim@sifive.com>2023-11-20 12:30:19 -0800
commit92213132a69a431e099c1f938963ef0152fabc3a (patch)
tree38d2fc9dc77250873d47f02cb5fe6964e3a660fc /doc
parentaf786c0eca6a3b845c8e6f2bb41fdc4ecbe83748 (diff)
parent18281b0c497694d91c5608be54583172838be75c (diff)
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Merge commit '18281b0c497694d91c5608be54583172838be75c' into from_upstream
Change-Id: I05cd5ef9b04fa61a27321ae9b6a4fecabe3dee80
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi73
-rw-r--r--doc/usb_adapters/angie/584e_424e_angie.txt59
2 files changed, 122 insertions, 10 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index c8a42f4..a2dacf2 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3597,6 +3597,79 @@ espusbjtag chip_id 1
@end deffn
+@deffn {Interface Driver} {dmem} Direct Memory access debug interface
+
+The Texas Instruments K3 SoC family provides memory access to DAP
+and coresight control registers. This allows control over the
+microcontrollers directly from one of the processors on the SOC
+itself.
+
+For maximum performance, the driver accesses the debug registers
+directly over the SoC memory map. The memory mapping requires read
+and write permission to kernel memory via "/dev/mem" and assumes that
+the system firewall configurations permit direct access to the debug
+memory space.
+
+@verbatim
++-----------+
+| OpenOCD | SoC mem map (/dev/mem)
+| on +--------------+
+| Cortex-A53| |
++-----------+ |
+ |
++-----------+ +-----v-----+
+|Cortex-M4F <--------+ |
++-----------+ | |
+ | DebugSS |
++-----------+ | |
+|Cortex-M4F <--------+ |
++-----------+ +-----------+
+@end verbatim
+
+NOTE: Firewalls are configurable in K3 SoC and depending on various types of
+device configuration, this function may be blocked out. Typical behavior
+observed in such cases is a firewall exception report on the security
+controller and armv8 processor reporting a system error.
+
+See @file{tcl/interface/ti_k3_am625-swd-native.cfg} for a sample configuration
+file.
+
+@deffn {Command} {dmem info}
+Print the DAPBUS dmem configuration.
+@end deffn
+
+@deffn {Config Command} {dmem device} device_path
+Set the DAPBUS memory access device (default: /dev/mem).
+@end deffn
+
+@deffn {Config Command} {dmem base_address} base_address
+Set the DAPBUS base address which is used to access CoreSight
+compliant Access Ports (APs) directly.
+@end deffn
+
+@deffn {Config Command} {dmem ap_address_offset} offset_address
+Set the address offset between Access Ports (APs).
+@end deffn
+
+@deffn {Config Command} {dmem max_aps} n
+Set the maximum number of valid access ports on the SoC.
+@end deffn
+
+@deffn {Config Command} {dmem emu_ap_list} n
+Set the list of Access Ports (APs) that need to be emulated. This
+emulation mode supports software translation of an AP request into an
+address mapped transaction that does not rely on physical AP hardware.
+This maybe needed if the AP is either denied access via memory map or
+protected using other SoC mechanisms.
+@end deffn
+
+@deffn {Config Command} {dmem emu_base_address_range} base_address address_window_size
+Set the emulated address and address window size. Both of these
+parameters must be aligned to page size.
+@end deffn
+
+@end deffn
+
@section Transport Configuration
@cindex Transport
As noted earlier, depending on the version of OpenOCD you use,
diff --git a/doc/usb_adapters/angie/584e_424e_angie.txt b/doc/usb_adapters/angie/584e_424e_angie.txt
index 8162cba..d68657a 100644
--- a/doc/usb_adapters/angie/584e_424e_angie.txt
+++ b/doc/usb_adapters/angie/584e_424e_angie.txt
@@ -1,13 +1,13 @@
# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later
-Bus 001 Device 056: ID 584e:424e NanoXplore, SAS. ANGIE Adapter
+Bus 001 Device 029: ID 584e:424e NanoXplore, SAS. ANGIE Adapter
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
- bDeviceClass 255 Vendor Specific Class
- bDeviceSubClass 255 Vendor Specific Subclass
- bDeviceProtocol 255 Vendor Specific Protocol
+ bDeviceClass 239 Miscellaneous Device
+ bDeviceSubClass 2
+ bDeviceProtocol 1 Interface Association
bMaxPacketSize0 64
idVendor 0x584e
idProduct 0x424e
@@ -19,13 +19,22 @@ Device Descriptor:
Configuration Descriptor:
bLength 9
bDescriptorType 2
- wTotalLength 0x0027
- bNumInterfaces 1
+ wTotalLength 0x0047
+ bNumInterfaces 2
bConfigurationValue 1
- iConfiguration 4 (error)
+ iConfiguration 1 NanoXplore, SAS.
bmAttributes 0x80
(Bus Powered)
MaxPower 100mA
+ Interface Association:
+ bLength 8
+ bDescriptorType 11
+ bFirstInterface 1
+ bInterfaceCount 2
+ bFunctionClass 2 Communications
+ bFunctionSubClass 0
+ bFunctionProtocol 0
+ iFunction 0
Interface Descriptor:
bLength 9
bDescriptorType 4
@@ -33,9 +42,9 @@ Device Descriptor:
bAlternateSetting 0
bNumEndpoints 3
bInterfaceClass 255 Vendor Specific Class
- bInterfaceSubClass 255 Vendor Specific Subclass
- bInterfaceProtocol 255 Vendor Specific Protocol
- iInterface 0
+ bInterfaceSubClass 0
+ bInterfaceProtocol 0
+ iInterface 4 JTAG Adapter
Endpoint Descriptor:
bLength 7
bDescriptorType 5
@@ -66,3 +75,33 @@ Device Descriptor:
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
+ Interface Descriptor:
+ bLength 9
+ bDescriptorType 4
+ bInterfaceNumber 1
+ bAlternateSetting 0
+ bNumEndpoints 2
+ bInterfaceClass 10 CDC Data
+ bInterfaceSubClass 0
+ bInterfaceProtocol 0
+ iInterface 0
+ Endpoint Descriptor:
+ bLength 7
+ bDescriptorType 5
+ bEndpointAddress 0x06 EP 6 OUT
+ bmAttributes 2
+ Transfer Type Bulk
+ Synch Type None
+ Usage Type Data
+ wMaxPacketSize 0x0200 1x 512 bytes
+ bInterval 0
+ Endpoint Descriptor:
+ bLength 7
+ bDescriptorType 5
+ bEndpointAddress 0x88 EP 8 IN
+ bmAttributes 2
+ Transfer Type Bulk
+ Synch Type None
+ Usage Type Data
+ wMaxPacketSize 0x0200 1x 512 bytes
+ bInterval 0