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| author | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-09 06:27:47 +0000 |
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| committer | oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-09-09 06:27:47 +0000 |
| commit | 8b2b0071a9a1f412a752da21542d4bcdaccd5751 (patch) | |
| tree | 19d1e9b9b5809304af8d183579dd9099d17c4bf5 /doc | |
| parent | 857c06ca8bc086d37fec5412f15b99ad37f229ac (diff) | |
| download | riscv-openocd-8b2b0071a9a1f412a752da21542d4bcdaccd5751.zip riscv-openocd-8b2b0071a9a1f412a752da21542d4bcdaccd5751.tar.gz riscv-openocd-8b2b0071a9a1f412a752da21542d4bcdaccd5751.tar.bz2 | |
David Brownell <david-b@pacbell.net>
Fix docs on ARM11 MCR and MRC coprocessor commands:
correct read-vs-write; and describe the params.
(ARM920 and ARM926 have cp15-specific commands; this
approach is more generic. MCR2, MRC2, MCRR, MCRR2,
MRRC, and MRRC2 instructions could also get exposed.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2679 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 183ec2d..62bb1eb 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5038,8 +5038,13 @@ Without arguments, the current settings are displayed. @subsection ARM11 specific commands @cindex ARM11 -@deffn Command {arm11 mcr} p1 p2 p3 p4 p5 -Read coprocessor register +@deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value +Write @var{value} to a coprocessor @var{pX} register +passing parameters @var{CRn}, +@var{CRm}, opcodes @var{opc1} and @var{opc2}, +and the MCR instruction. +(The difference beween this and the MCR2 instruction is +one bit in the encoding, effecively a fifth parameter.) @end deffn @deffn Command {arm11 memwrite burst} [value] @@ -5054,8 +5059,13 @@ which is enabled by default. If @var{value} is defined, first assigns that. @end deffn -@deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value -Write coprocessor register +@deffn Command {arm11 mrc} pX opc1 CRn CRm opc2 +Read a coprocessor @var{pX} register passing parameters @var{CRn}, +@var{CRm}, opcodes @var{opc1} and @var{opc2}, +and the MRC instruction. +(The difference beween this and the MRC2 instruction is +one bit in the encoding, effecively a fifth parameter.) +Displays the result. @end deffn @deffn Command {arm11 no_increment} [value] |