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| author | Samuel Obuch <sobuch@codasip.com> | 2020-10-01 20:05:41 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-01 11:05:41 -0700 |
| commit | 6db3ed2c862e04588bf80758acb463a14e9b5ff5 (patch) | |
| tree | 9efd1449105d04977f26761c1bcc448270923d82 /doc | |
| parent | 2c909f8faae052ccc3cec82ed0d98b043f871ce3 (diff) | |
| download | riscv-openocd-6db3ed2c862e04588bf80758acb463a14e9b5ff5.zip riscv-openocd-6db3ed2c862e04588bf80758acb463a14e9b5ff5.tar.gz riscv-openocd-6db3ed2c862e04588bf80758acb463a14e9b5ff5.tar.bz2 | |
Improve riscv expose_[csrs|custom] commands (#536)
* Improve riscv expose_[csrs|custom] commands
* Add option to specify custom name for registers.
* Allow to call commands multiple times without loss of previous data.
* Make sure the commands can only be used in the config phase (before "init").
* Validity checks and warnings.
* Change commands to be per target.
* Fix memory leaks.
* Also fix unrelated memory leaks to keep valgrind happy.
Signed-off-by: Samuel Obuch <sobuch@codasip.com>
* fixes after review
* improve error message
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 790955d..fb0b286 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -9641,9 +9641,11 @@ OpenOCD exposes each hart as a separate core. @subsection RISC-V Debug Configuration Commands -@deffn Command {riscv expose_csrs} n0[-m0][,n1[-m1]]... -Configure a list of inclusive ranges for CSRs to expose in addition to the -standard ones. This must be executed before `init`. +@deffn Command {riscv expose_csrs} n[-m|=name] [...] +Configure which CSRs to expose in addition to the standard ones. The CSRs to expose +can be specified as individual register numbers or register ranges (inclusive). For the +individually listed CSRs, a human-readable name can optionally be set. +This command must be executed before `init`. By default OpenOCD attempts to expose only CSRs that are mentioned in a spec, and then only if the corresponding extension appears to be implemented. This @@ -9651,11 +9653,12 @@ command can be used if OpenOCD gets this wrong, or a target implements custom CSRs. @end deffn -@deffn Command {riscv expose_custom} n0[-m0][,n1[-m1]]... +@deffn Command {riscv expose_custom} n[-m|=name] [...] The RISC-V Debug Specification allows targets to expose custom registers through abstract commands. (See Section 3.5.1.1 in that document.) This command -configures a list of inclusive ranges of those registers to expose. Number 0 -indicates the first custom register, whose abstract command number is 0xc000. +configures individual registers or register ranges (inclusive) that shall be exposed. +Number 0 indicates the first custom register, whose abstract command number is 0xc000. +For individually listed registers, a human-readable name can be optionally provided. This command must be executed before `init`. @end deffn |