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| author | Christopher Head <chead@zaber.com> | 2019-04-01 16:06:30 -0700 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2019-04-10 10:10:25 +0100 |
| commit | 487710da6d65e1704f68849a152fec76752d4f4e (patch) | |
| tree | 2acda1b7eafca56bab40736f9ecfb0a846533ab2 /doc | |
| parent | 1f4596cc46c96471f32d81613a612a4adefe36ab (diff) | |
| download | riscv-openocd-487710da6d65e1704f68849a152fec76752d4f4e.zip riscv-openocd-487710da6d65e1704f68849a152fec76752d4f4e.tar.gz riscv-openocd-487710da6d65e1704f68849a152fec76752d4f4e.tar.bz2 | |
Document the mem_ap target type
Change-Id: I56e971b38f20db8c4ad0cdee5cc42b42a25319ea
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/5029
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 027e6d2..f5852cc 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4367,6 +4367,7 @@ compact Thumb2 instruction set. The current implementation supports eSi-32xx cores. @item @code{fa526} -- resembles arm920 (w/o Thumb) @item @code{feroceon} -- resembles arm926 +@item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without a CPU, through which bus read and write cycles can be generated; it may be useful for working with non-CPU hardware behind an AP or during development of support for new CPUs. @item @code{mips_m4k} -- a MIPS core @item @code{xscale} -- this is actually an architecture, not a CPU type. It is based on the ARMv5 architecture. |