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authorianst <ianst@cadence.com>2023-11-09 07:28:50 -0800
committerAntonio Borneo <borneo.antonio@gmail.com>2023-11-18 11:18:29 +0000
commitf8096ce68724d15d0ef9a7edfd6d2aaa0f83a6e5 (patch)
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parent9ebc2a65191308d3677a84ebbbdad97a93eae7de (diff)
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xtensa: update XDM register map for TRAX support
- Include additional debug module registers - Add translation function for DM reg addr -> ID - Add DM read/write commands Signed-off-by: ianst <ianst@cadence.com> Change-Id: If95419d24a9f27a40fa695c8c15326cdfd127ef1 Reviewed-on: https://review.openocd.org/c/openocd/+/7973 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
Diffstat (limited to 'doc/openocd.texi')
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1 files changed, 6 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4eb911c..b03da4f 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11487,6 +11487,12 @@ Execute arbitrary instruction(s) provided as an ascii string. The string repres
number of instruction bytes, thus its length must be even.
@end deffn
+@deffn {Command} {xtensa dm} (address) [value]
+Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads
+and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified
+only for write accesses.
+@end deffn
+
@subsection Xtensa Performance Monitor Configuration
@deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]