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author | Marek Vasut <marek.vasut@gmail.com> | 2021-06-12 20:48:51 +0200 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-06-26 14:39:22 +0100 |
commit | a38a0afd17d943b8bbc046f5fcfbf150871557a2 (patch) | |
tree | e39314f69727807ad19ad4d4e1737a153bf4224b /README | |
parent | 0ef5144c32ac60ddf3bb005deb3136015e42ae4f (diff) | |
download | riscv-openocd-a38a0afd17d943b8bbc046f5fcfbf150871557a2.zip riscv-openocd-a38a0afd17d943b8bbc046f5fcfbf150871557a2.tar.gz riscv-openocd-a38a0afd17d943b8bbc046f5fcfbf150871557a2.tar.bz2 |
tcl/target: Select default boot core on Renesas R-Car Gen2/Gen3
On SMP Renesas R-Car Gen2/Gen3 systems, select the boot core as
the default target using the 'targets' command. This way, the
user can start debugging code running on the boot core without
having to switch to the boot core by explicitly invoking 'targets'
command first, since it is likely the debugged code will run on
the boot core. Note that most of the code is already in place, it
was just not used, so this is more of a fix to make the original
intention work.
Change-Id: I727808adce617c1d9ebd6ffa34f60f5882cdae60
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/6313
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'README')
0 files changed, 0 insertions, 0 deletions